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1. 发明申请

US20120164802A1 ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS 有权
标题翻译：高级CMOS使用超级梯形变压器
公开(公告)号：US20120164802A1
公开(公告)日：2012-06-28
申请号：US13359125
申请日：2012-01-26
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

2. 发明授权

US08203197B2 Thermally enhanced semiconductor devices 有权
标题翻译：热增强半导体器件
公开(公告)号：US08203197B2
公开(公告)日：2012-06-19
申请号：US12758610
申请日：2010-04-12
申请人： Leland Scott Swanson , Gregory E. Howard
发明人： Leland Scott Swanson , Gregory E. Howard
IPC分类号： H01L21/70
CPC分类号： H01L27/0211
摘要： Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.
摘要翻译：形成在第一和第二有源衬底区域的较低电阻子区域中的匹配晶体管的热通信由形成为在第一和第二区域的较高电阻子区域之间的隔离区域上延伸的导热构件提供。在一种形式中，通过绝缘层与在衬底上形成的金属层进行热连通，具有或不具有触点。在另一种形式中，通过在衬底上形成的多晶硅层进行热连通。

3. 发明授权

US08053873B2 IC having voltage regulated integrated Faraday shield 有权
标题翻译： IC具有电压调节集成法拉第屏蔽
公开(公告)号：US08053873B2
公开(公告)日：2011-11-08
申请号：US12477002
申请日：2009-06-02
申请人： Satyendra S Chauhan , Gregory E Howard
发明人： Satyendra S Chauhan , Gregory E Howard
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L23/481 , H01L25/0657 , H01L25/16 , H01L2224/05009 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2225/06513 , H01L2924/00014 , H01L2224/05599
摘要： An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.
摘要翻译：集成电路（IC）包括具有顶部半导体表面和底部表面的基板，以及集成电路，其包括形成在顶部半导体表面上的模拟子电路和至少一个数字子电路。多个通过衬底通孔（TSV）延伸穿过衬底。至少一个集成法拉第屏蔽包括由围绕模拟子电路和/或数字子电路的TSV耦合的顶部和底部导电构件。至少一个电压调节器提供稳定的电源电压，其耦合到围绕模拟子电路的集成法拉第屏蔽。

4. 发明申请

US20100193909A1 THERMALLY ENHANCED SEMICONDUCTOR DEVICES 有权
标题翻译：热增强半导体器件
公开(公告)号：US20100193909A1
公开(公告)日：2010-08-05
申请号：US12758610
申请日：2010-04-12
申请人： Leland Scott Swanson , Gregory E. Howard
发明人： Leland Scott Swanson , Gregory E. Howard
IPC分类号： H01L27/06 , H01L29/86
CPC分类号： H01L27/0211
摘要： Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.
摘要翻译：形成在第一和第二有源衬底区域的较低电阻子区域中的匹配晶体管的热通信由形成为在第一和第二区域的较高电阻子区域之间的隔离区域上延伸的导热构件提供。在一种形式中，通过绝缘层与在衬底上形成的金属层进行热连通，具有或不具有触点。在另一种形式中，通过在衬底上形成的多晶硅层进行热连通。

5. 发明申请

US20090267218A1 Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area 有权
公开(公告)号：US20090267218A1
公开(公告)日：2009-10-29
申请号：US12499182
申请日：2009-07-08
申请人： Vikas GUPTA , Siva P. GURRUM , Gregory E. HOWARD
发明人： Vikas GUPTA , Siva P. GURRUM , Gregory E. HOWARD
IPC分类号： H01L23/36 , H01L23/52
CPC分类号： H01L23/3677 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/73265 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/181 , H01L2924/20751 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/01004 , H01L2924/01026 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012
摘要： A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

6. 发明授权

US07199430B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US07199430B2
公开(公告)日：2007-04-03
申请号：US11362908
申请日：2006-02-28
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

7. 发明授权

US06927428B2 Lateral heterojunction bipolar transistor 有权
标题翻译：横向异质结双极晶体管
公开(公告)号：US06927428B2
公开(公告)日：2005-08-09
申请号：US10818931
申请日：2004-04-06
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard
IPC分类号： H01L21/84 , H01L27/12 , H01L29/423 , H01L29/73 , H01L29/737
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42304 , H01L29/7317
摘要： A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (6) overlying the buried insulator layer (4). A base electrode (10) is formed of polysilicon, and has a polysilicon filament (10f) that extends over the edge of an insulator layer (8) to contact the silicon layer (6). After formation of insulator filaments (12) along the edges of the base electrode (10) and insulator layer (8), the thin film silicon layer (6) is etched through, exposing an edge. An angled ion implantation then implants the heterojunction species, for example germanium and carbon, into the exposed edge of the thin film silicon layer (6), which after anneal forms the heterojunction base region (20). Polysilicon plugs for the emitter (24e) and collector (24c) are then formed, from which dopant diffuses to form the intrinsic emitter (25) and subcollector (22) of the device.
摘要翻译：公开了一种绝缘体上硅（SOI）结构中的异质结双极晶体管（30）。在覆盖在掩埋绝缘体层（4）上的薄膜硅层（6）中形成晶体管集电极（28），异质结基极区（20）和本征发射极区（25）。基极（10）由多晶硅形成，并且具有在绝缘体层（8）的边缘上延伸以接触硅层（6）的多晶硅细丝（10f）。沿着基极（10）和绝缘体层（8）的边缘形成绝缘体细丝（12）之后，将薄膜硅层（6）蚀刻通过边缘露出。然后，成角度的离子注入将异质结物质（例如锗和碳）注入到薄膜硅层（6）的暴露边缘中，其在退火后形成异质结基极区域（20）。然后形成用于发射极（24e）和集电极（24c）的多晶硅插头，掺杂剂从该多晶硅插塞扩散以形成器件的本征发射极（25）和子集电极（22）。

8. 发明授权

US06905932B2 Method for constructing a metal oxide semiconductor field effect transistor 有权
标题翻译：金属氧化物半导体场效应晶体管的构成方法
公开(公告)号：US06905932B2
公开(公告)日：2005-06-14
申请号：US10719198
申请日：2003-11-21
申请人： Gregory E. Howard , Jeffrey Babcock , Angelo Pinto
发明人： Gregory E. Howard , Jeffrey Babcock , Angelo Pinto
IPC分类号： H01L21/336 , H01L29/161 , H01L21/331 , H01L21/44 , H01L21/4763
CPC分类号： H01L29/66583 , H01L29/161 , H01L29/66651
摘要： A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).
摘要翻译：公开了半导体器件（100）和构造半导体器件（100）的方法。在半导体层（108）的外表面附近形成沟槽隔离结构（112）和有源区（110）。外延层（111）从沟槽隔离结构（112）向外沉积。在外延层（111）附近生长第一绝缘体层（116）和第二绝缘体层（118）。包括第一绝缘体层（116和第二绝缘体层118的部分）的栅极叠层（123）从外延层（111）向外形成，栅极叠层（123）还包括具有栅极窄区域（130）和形成在第二绝缘体层（118）附近的宽区域（132）。外延层（111）被加热到足以允许外延层（111）形成源极/漏极注入区域（126）在有源区（110）中。

9. 发明授权

US06873040B2 Semiconductor packages for enhanced number of terminals, speed and power performance 有权
标题翻译：半导体封装，增加端子数，速度和功率性能
公开(公告)号：US06873040B2
公开(公告)日：2005-03-29
申请号：US10614851
申请日：2003-07-08
申请人： Gregory E. Howard , Mukul Saran
发明人： Gregory E. Howard , Mukul Saran
IPC分类号： H01L23/13 , H01L23/498 , H01L23/48
CPC分类号： H01L24/73 , H01L23/13 , H01L23/49816 , H01L23/49833 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit device package with a first part (101) having a cavity (104) to mount the chip (105), further I/O terminals (102) on the top surface and terminals (103) on the bottom surface. The chip has contact pads (107a and 107b). The second part (110) of the package has bottom surface terminals (111) aligned with the chip contact pads, and bottom terminals (112) aligned with the terminals (102) of the first package part. The connections are provided by stud bumps between the chip contact pads and terminals (111), and by reflow material between terminals (102) and (1.12). The connector lines (109a and 109b) in the second package part (110) comprise signal/power and ground layers. The layers are spaced by insulation between. 10 and 50 μm thick, and the connector lines have a width less than three times the insulator thickness.
摘要翻译：一种具有第一部分（101）的集成电路器件封装，其具有用于安装芯片（105）的空腔（104），在顶表面上的另外的I / O端子（102）和底表面上的端子（103）。芯片具有接触焊盘（107a和107b）。封装的第二部分（110）具有与芯片接触焊盘对准的底表面端子（111）和与第一封装部件的端子（102）对准的底部端子（112）。连接由芯片接触焊盘和端子（111）之间的螺柱凸起以及端子（102）和（1.12）之间的回流材料提供。第二封装部分（110）中的连接器线（109a和109b）包括信号/功率和接地层。这些层之间的绝缘间隔开。 10和50μm厚，并且连接器线具有小于绝缘体厚度的三倍的宽度。

10. 发明授权

US06680504B2 Method for constructing a metal oxide semiconductor field effect transistor 有权
标题翻译：金属氧化物半导体场效应晶体管的构成方法
公开(公告)号：US06680504B2
公开(公告)日：2004-01-20
申请号：US10020604
申请日：2001-12-14
申请人： Gregory E. Howard , Jeffrey Babcock , Angelo Pinto
发明人： Gregory E. Howard , Jeffrey Babcock , Angelo Pinto
IPC分类号： H01L27108
CPC分类号： H01L29/66583 , H01L29/161 , H01L29/66651
摘要： A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).
摘要翻译：公开了半导体器件（100）和构造半导体器件（100）的方法。在半导体层（108）的外表面附近形成沟槽隔离结构（112）和有源区（110）。外延层（111）从沟槽隔离结构（112）向外沉积。在外延层（111）附近生长第一绝缘体层（116）和第二绝缘体层（118）。包括第一绝缘体层（116和第二绝缘体层118的部分）的栅极叠层（123）从外延层（111）向外形成，栅极叠层（123）还包括具有栅极窄区域（130）和形成在第二绝缘体层（118）附近的宽区域（132）。外延层（111）被加热到足以允许外延层（111）形成源极/漏极注入区域（126）在有源区（110）中。

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