专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060265556A1 System and method for decoding commands based on command signals and operating state 有权
标题翻译：基于命令信号和操作状态对命令进行解码的系统和方法
公开(公告)号：US20060265556A1
公开(公告)日：2006-11-23
申请号：US11121868
申请日：2005-05-03
申请人： Jeffery Janzen , Brent Keeth , Jeffrey Wright , James Cullum
发明人： Jeffery Janzen , Brent Keeth , Jeffrey Wright , James Cullum
IPC分类号： G06F13/00
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译：一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。

2. 发明申请

US20050094432A1 Multi-mode synchronous memory device and methods of operating and testing same 失效
标题翻译：多模同步存储器件及其操作和测试方法相同
公开(公告)号：US20050094432A1
公开(公告)日：2005-05-05
申请号：US11001231
申请日：2004-12-01
申请人： Brian Johnson , Brent Keeth , Jeffery Janzen , Troy Manning , Chris Martin
发明人： Brian Johnson , Brent Keeth , Jeffery Janzen , Troy Manning , Chris Martin
IPC分类号： G01R31/28 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C29/14 , G11C11/00
CPC分类号： G11C29/12015 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C29/14
摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.
摘要翻译：同步半导体存储器件可以在正常模式和替代模式下操作。半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作模式使用具有小于预定最小频率的频率的外部时钟信号。替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

3. 发明申请

US20210240344A1 WAFER-SCALE MEMORY TECHNIQUES 有权
公开(公告)号：US20210240344A1
公开(公告)日：2021-08-05
申请号：US17162796
申请日：2021-01-29
申请人： Brent Keeth , Bambi L. DeLaRosa , Eiichi Nakano
发明人： Brent Keeth , Bambi L. DeLaRosa , Eiichi Nakano
IPC分类号： G06F3/06
摘要： Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

4. 发明申请

US20210200464A1 MEMORY DEVICE INTERFACE AND METHOD 有权
公开(公告)号：US20210200464A1
公开(公告)日：2021-07-01
申请号：US17136728
申请日：2020-12-29
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G06F3/06
摘要： Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

5. 发明授权

US09214449B2 Reconfigurable connections for stacked semiconductor devices 有权
标题翻译：层叠半导体器件的可重构连接
公开(公告)号：US09214449B2
公开(公告)日：2015-12-15
申请号：US13367026
申请日：2012-02-06
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/26 , H01L25/065 , G11C5/02 , G11C5/06 , G11C29/02 , G11C29/00 , G11C5/04 , G11C29/32
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接的缺陷。

6. 发明授权

US08712249B2 Optical interconnect in high-speed memory systems 有权
标题翻译：高速存储器系统中的光互连
公开(公告)号：US08712249B2
公开(公告)日：2014-04-29
申请号：US13080376
申请日：2011-04-05
申请人： Russel J. Baker , Brent Keeth
发明人： Russel J. Baker , Brent Keeth
IPC分类号： H04B10/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/1668 , G06F13/287 , G06F13/4234 , G11C11/42 , H04B10/802 , H04L12/40013 , H04Q11/0071 , Y02D10/14 , Y02D10/151
摘要： A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.
摘要翻译：公开了一种用于实现控制器和存储器件之间的电气隔离的光学链路。光链路增加了电互连的抗噪声能力，并且允许存储器件被放置在距离处理器更远的位置，而不需要耗电的I / O缓冲器。

7. 发明申请

US20120246434A1 SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 有权
标题翻译：基于命令信号和操作状态解码命令的系统和方法
公开(公告)号：US20120246434A1
公开(公告)日：2012-09-27
申请号：US13489246
申请日：2012-06-05
申请人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
发明人： Jeffrey W. Janzen , Brent Keeth , Jeffrey P. Wright , James S. Cullum
IPC分类号： G06F12/00
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译：一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态执行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。

8. 发明申请

US20120133387A1 RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES 有权
标题翻译：堆叠式半导体器件的可重构连接
公开(公告)号：US20120133387A1
公开(公告)日：2012-05-31
申请号：US13367026
申请日：2012-02-06
申请人： Brent Keeth
发明人： Brent Keeth
IPC分类号： G01R31/26
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/06 , G11C29/02 , G11C29/022 , G11C29/70 , G11C2029/3202 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1531 , H01L2924/00
摘要： Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
摘要翻译：一些实施例包括包括布置在堆叠中的半导体裸片的装置，系统和方法，被配置为提供骰子之间的通信的多个连接，穿过至少一个骰子的连接的至少一部分，以及被配置为检查连接中的缺陷并修复连接中的缺陷。

9. 发明申请

US20110261628A1 256 Meg dynamic random access memory 失效
公开(公告)号：US20110261628A1
公开(公告)日：2011-10-27
申请号：US13135066
申请日：2011-06-24
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

10. 发明授权

US07969810B2 256 Meg dynamic random access memory 有权
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US07969810B2
公开(公告)日：2011-06-28
申请号：US12381143
申请日：2009-03-06
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于来自每个象限的数据，将数据输出到数据读取复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式