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1. 发明申请

US20110261628A1 256 Meg dynamic random access memory 失效
公开(公告)号：US20110261628A1
公开(公告)日：2011-10-27
申请号：US13135066
申请日：2011-06-24
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

2. 发明授权

US07969810B2 256 Meg dynamic random access memory 有权
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US07969810B2
公开(公告)日：2011-06-28
申请号：US12381143
申请日：2009-03-06
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于来自每个象限的数据，将数据输出到数据读取复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

3. 发明申请

US20210201966A1 MEMORY MODULE MUTIPLE PORT BUFFER TECHNIQUES 有权
公开(公告)号：US20210201966A1
公开(公告)日：2021-07-01
申请号：US17137975
申请日：2020-12-30
申请人： Jasper S. Gibbons , Matthew A. Prather , Brent Keeth , Frank F. Ross , Daniel Benjamin Stewart , Randall J. Rooney
发明人： Jasper S. Gibbons , Matthew A. Prather , Brent Keeth , Frank F. Ross , Daniel Benjamin Stewart , Randall J. Rooney
IPC分类号： G11C7/10 , G11C7/22
摘要： The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

4. 发明申请

US20090245009A1 256 Meg dynamic random access memory 有权
公开(公告)号：US20090245009A1
公开(公告)日：2009-10-01
申请号：US12381143
申请日：2009-03-06
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

5. 发明授权

US06324088B1 256 meg dynamic random access memory 有权
标题翻译： 256兆动态随机存取存储器
公开(公告)号：US06324088B1
公开(公告)日：2001-11-27
申请号：US09621012
申请日：2000-07-20
申请人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
发明人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
IPC分类号： G11C502
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

6. 发明申请

US20210200699A1 NEUROMORPHIC MEMORY DEVICE AND METHOD 有权
公开(公告)号：US20210200699A1
公开(公告)日：2021-07-01
申请号：US17131217
申请日：2020-12-22
申请人： Brent Keeth , Frank F Ross , Richard C Murphy
发明人： Brent Keeth , Frank F Ross , Richard C Murphy
IPC分类号： G06F13/16 , G06N3/00 , H01L25/065 , H01L25/18
摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.

7. 发明授权

US08189423B2 256 Meg dynamic random access memory 失效
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US08189423B2
公开(公告)日：2012-05-29
申请号：US13135066
申请日：2011-06-24
申请人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
发明人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。组合多个电源以将其功率输出与功率需求相匹配并且保持所需的功率产生能力和去耦电容的比率。提供上电序列电路以控制芯片的上电。

8. 发明授权

US07489564B2 256 Meg dynamic random access memory 失效
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US07489564B2
公开(公告)日：2009-02-10
申请号：US11452819
申请日：2006-06-14
申请人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
发明人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于来自每个象限的数据，将数据输出到数据读取复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

9. 发明授权

US07477556B2 256 Meg dynamic random access memory 失效
公开(公告)号：US07477556B2
公开(公告)日：2009-01-13
申请号：US09899977
申请日：2001-07-06
申请人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
发明人： Brent Keeth , Layne G. Bunker , Raymond J. Beffa , Frank F. Ross
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

10. 发明授权

US06314011B1 256 Meg dynamic random access memory 失效
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US06314011B1
公开(公告)日：2001-11-06
申请号：US08916692
申请日：1997-08-22
申请人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C502
CPC分类号： H01L27/10805
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

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