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1. 发明授权

US5846871A Integrated circuit fabrication 失效
标题翻译：集成电路制造
公开(公告)号：US5846871A
公开(公告)日：1998-12-08
申请号：US918394
申请日：1997-08-26
申请人： Jean Ling Lee , Yi Ma , Sailesh Mansinh Merchant
发明人： Jean Ling Lee , Yi Ma , Sailesh Mansinh Merchant
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L21/283
CPC分类号： H01L21/823835 , H01L21/28061
摘要： Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.
摘要翻译：例如通过穿过上覆硅化物的交叉扩散，n + / p +门的不期望的反向掺杂被多晶硅栅极和覆盖的硅化物之间插入氮化钛和钛，钨或钽层。

2. 发明授权

US06320238B1 Gate structure for integrated circuit fabrication 有权
标题翻译：集成电路制造的门结构
公开(公告)号：US06320238B1
公开(公告)日：2001-11-20
申请号：US09339895
申请日：1999-06-25
申请人： Isik C. Kizilyalli , Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Isik C. Kizilyalli , Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
摘要翻译：本发明涉及一种具有设置在其上设置有栅电极的基板上的电介质材料层的栅极堆叠结构。在一个示例性实施例中，电介质材料层具有2.2nm或更小的等效电气厚度，并且包括除二氧化硅之外的至少一个层。此外，本发明的电介质材料层能够进行器件定标，并且与常规栅极电介质相比提供（1）降低的漏电流和改善的隧穿电压; 和（2）当专门用作栅极电介质时，避免超薄二氧化硅的危险。

3. 发明授权

US5981403A Layered silicon nitride deposition process 失效
标题翻译：分层氮化硅沉积工艺
公开(公告)号：US5981403A
公开(公告)日：1999-11-09
申请号：US977319
申请日：1997-11-24
申请人： Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Yi Ma , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L21/28 , H01L21/314 , H01L21/318 , H01L21/32 , H01L21/762 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/3145 , H01L21/3185 , H01L21/32 , H01L21/76202 , H01L29/513 , H01L29/518
摘要： A semiconductor device process for forming a multilayered nitride structure. The nitride is used as either isolation or as part of a dielectric structure. The deposition rate for the nitride is varied to form a multilayered structure with stress accommodation at the interface between sub-layers in the multilayer structure. In addition, the sub-layered structure reduces pin-holes and microcracks in the nitride film and improves the overall uniformity in thickness of the final nitride film.
摘要翻译：一种用于形成多层氮化物结构的半导体器件工艺。氮化物被用作隔离或作为电介质结构的一部分。改变氮化物的沉积速率以形成在多层结构中的子层之间的界面处具有应力调节的多层结构。此外，亚层结构减少氮化物膜中的针孔和微裂纹，并且改善最终氮化物膜的厚度的总体均匀性。

4. 发明授权

US06147388A Polycide gate structure with intermediate barrier 失效
标题翻译：具有中间屏障的聚酰胺门结构
公开(公告)号：US06147388A
公开(公告)日：2000-11-14
申请号：US977318
申请日：1997-11-24
申请人： Yi Ma , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy
发明人： Yi Ma , Sailesh Mansinh Merchant , Minseok Oh , Pradip Kumar Roy
IPC分类号： H01L29/78 , H01L21/28 , H01L21/324 , H01L21/8238 , H01L27/092 , H01L29/43 , H01L29/49 , H01L21/283 , H01L21/265
CPC分类号： H01L21/324 , H01L21/28061 , H01L29/4925 , H01L29/4941
摘要： A CMOS gate structure comprises a multilayered polysilicon structure and a deposited silicide layer, with a nitridized silicide barrier layer formed therebetween. The multilayered polysilicon will exhibit a relatively large grain size and uniform structure. The deposited silicide layer is annealed to mimic the polysilicon grain size and structure. The combination of the tailored grain structure with the intermediate barrier layer results in a gate structure that is essentially impervious to subsequent dopant diffusions.
摘要翻译： CMOS栅极结构包括多层多晶硅结构和沉积的硅化物层，其间形成氮化硅化物阻挡层。多层多晶硅将具有相对较大的晶粒尺寸和均匀的结构。将沉积的硅化物层退火以模拟多晶硅晶粒尺寸和结构。定制的晶粒结构与中间阻挡层的组合导致栅极结构，其基本上不渗透随后的掺杂剂扩散。

5. 发明授权

US5950096A Process for improving device yield in integrated circuit fabrication 失效
标题翻译：在集成电路制造中提高器件产量的工艺
公开(公告)号：US5950096A
公开(公告)日：1999-09-07
申请号：US935362
申请日：1997-09-22
申请人： Robert Y.S. Huang , David Kou-Fong Hwang , Stephen Carl Kuehne , Jean Ling Lee , Jane Qian Liu , Yi Ma , Minseok Oh
发明人： Robert Y.S. Huang , David Kou-Fong Hwang , Stephen Carl Kuehne , Jean Ling Lee , Jane Qian Liu , Yi Ma , Minseok Oh
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： In the fabrication of an integrated circuit, undesirable bird's beak pull back due to damage caused during ion implantation is alleviated by means of rapid thermal annealing step prior to chemical etching.
摘要翻译：在集成电路的制造中，由化学蚀刻之前的快速热退火步骤减轻了离子注入过程中造成的损坏引起的不希望有的鸟喙拉回。

6. 发明授权

US08818132B2 Camera calibration with lens distortion from low-rank textures 有权
标题翻译：相机校准与低等级纹理的镜头失真
公开(公告)号：US08818132B2
公开(公告)日：2014-08-26
申请号：US13310729
申请日：2011-12-03
申请人： Zhengdong Zhang , Yasuyuki Matsushita , Yi Ma
发明人： Zhengdong Zhang , Yasuyuki Matsushita , Yi Ma
IPC分类号： G06K9/36 , G06T7/00
CPC分类号： G06T7/0018 , G06T7/80 , G06T2207/20104 , H04N17/002
摘要： A “Camera Calibrator” provides various techniques for recovering intrinsic camera parameters and distortion characteristics by processing a set of one or more input images. These techniques are based on extracting “Transform Invariant Low-Rank Textures” (TILT) from input images using high-dimensional convex optimization tools for matrix rank minimization and sparse signal recovery. The Camera Calibrator provides a simple, accurate, and flexible method to calibrate intrinsic parameters of a camera even with significant lens distortion, noise, errors, partial occlusions, illumination and viewpoint change, etc. Distortions caused by the camera can then be automatically corrected or removed from images. Calibration is achieved under a wide range of practical scenarios, including using multiple images of a known pattern, multiple images of an unknown pattern, single or multiple images of multiple patterns, etc. Significantly, calibration is achieved without extracting or manually identifying low-level features such as corners or edges from the calibration images.
摘要翻译： “相机校准器”提供了通过处理一组一个或多个输入图像来恢复本征相机参数和失真特性的各种技术。这些技术基于使用用于矩阵秩最小化和稀疏信号恢复的高维凸优化工具从输入图像中提取“变换不变低阶纹理”（TILT）。相机校准器提供了一种简单，准确和灵活的校准相机内在参数的方法，即使有明显的镜头失真，噪点，错误，部分遮挡，照明和视点更改等。然后可以自动更正相机造成的失真或从图像中删除在广泛的实际情况下实现校准，包括使用已知图案的多个图像，未知图案的多个图像，多个图案的单个或多个图像等。显着地，在不提取或手动识别低级别的情况下实现校准特征如校准图像的拐角或边缘。

7. 发明授权

US08426839B1 Conducting bridge random access memory (CBRAM) device structures 有权
标题翻译：传导桥随机存取存储器（CBRAM）器件结构
公开(公告)号：US08426839B1
公开(公告)日：2013-04-23
申请号：US12767552
申请日：2010-04-26
申请人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
发明人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
IPC分类号： H01L45/00 , H01L29/04 , H01L29/12
CPC分类号： H01L45/085 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/1608 , H01L45/165 , H01L45/1658 , H01L45/1675 , H01L45/1683
摘要： A conductive bridging memory cell may include an ion conductor layer formed over an active electrode that is a source of conductive ions for the ion conductor; a conductive layer; and a barrier layer formed below the active layer and in contact with the conductive, the barrier layer substantially preventing a movement of conductive ions therethrough.
摘要翻译：导电桥接存储单元可以包括在作为离子导体的导电离子源的有源电极上形成的离子导体层; 导电层; 以及形成在有源层下方并与导体接触的阻挡层，阻挡层基本上防止导电离子通过其移动。

8. 发明授权

US07871942B2 Methods for manufacturing high dielectric constant film 有权
标题翻译：制造高介电常数膜的方法
公开(公告)号：US07871942B2
公开(公告)日：2011-01-18
申请号：US12057113
申请日：2008-03-27
申请人： Shreyas S. Kher , Pravin K. Narwankar , Khaled Z. Ahmed , Yi Ma
发明人： Shreyas S. Kher , Pravin K. Narwankar , Khaled Z. Ahmed , Yi Ma
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31645 , C23C14/083 , C23C16/56 , H01L21/3141
摘要： Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.
摘要翻译：公开了使用含有超高纯度铪的有机金属化合物制造高K（介电常数）膜的方法。还描述了包含用高纯度铪含有有机金属化合物制成的高K膜的装置。

9. 发明授权

US07659158B2 Atomic layer deposition processes for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的原子层沉积工艺
公开(公告)号：US07659158B2
公开(公告)日：2010-02-09
申请号：US12059782
申请日：2008-03-31
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.
摘要翻译：本发明的实施例提供了用于形成存储器件的存储器件和方法。在一个实施例中，提供了一种存储器件，其包括设置在衬底的源极/漏极区域上的浮置栅极多晶硅层，设置在浮置栅极多晶硅层上的氧氮化硅层，设置在氧氮化硅层上的第一氧化铝层，设置在所述第一氧化铝层上的铪硅氮化物层，设置在所述铪硅氮氧化物层上的第二氧化铝层，以及设置在所述第二氧化铝层上的控制栅极多晶硅层。在另一个实施例中，提供了一种存储器件，其包括设置在布置在浮置多晶硅层上方的氧化硅层上的多晶硅介质叠层之间的控制栅极多晶硅层。多晶硅间介质堆叠包含由氮化硅层分隔的两个氮氧化硅层。

10. 发明授权

US07602067B2 Hetero-structure variable silicon rich nitride for multiple level memory flash memory device 失效
标题翻译：异质结构可变富硅氮化物用于多级存储器闪存器件
公开(公告)号：US07602067B2
公开(公告)日：2009-10-13
申请号：US11957787
申请日：2007-12-17
申请人： Yi Ma , Robert Ogle
发明人： Yi Ma , Robert Ogle
IPC分类号： H01L29/40
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42348 , H01L29/7923
摘要： Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n−1th charge storage layer is higher than a k-value of an nth charge storage layer; n−1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers.
摘要翻译：提供了包含用于存储单元的异质结构可变富硅氮化物的电荷存储堆，以及用于制造电荷存储堆的方法。电荷存储堆可以包含半导体衬底上的第一绝缘层; n在第一绝缘层上形成包括富硅氮化物的存储层，其中电荷存储层的数量从底部增加到顶部，并且第n-1个电荷存储层的k值高于k值的第n电荷存储层; n-1个电介质层，其在n个电荷存储层中的每一个之间包含基本上化学计量的氮化硅; 以及第n电荷存储层上的第二绝缘层。

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