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1. 发明授权

US07995472B2 Flexible network processor scheduler and data flow 失效
标题翻译：灵活的网络处理器调度器和数据流
公开(公告)号：US07995472B2
公开(公告)日：2011-08-09
申请号：US12348938
申请日：2009-01-06
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： G01R31/08 , H04L12/28 , H04L12/54
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

2. 发明授权

US07483429B2 Method and system for flexible network processor scheduler and data flow 失效
标题翻译：灵活的网络处理器调度器和数据流的方法和系统
公开(公告)号：US07483429B2
公开(公告)日：2009-01-27
申请号：US11133477
申请日：2005-05-18
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： H04L12/56 , H04J3/24 , G06F15/00
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

3. 发明申请

US20090175275A1 FLEXIBLE NETWORK PROCESSOR SCHEDULER AND DATA FLOW 失效
标题翻译：灵活的网络处理器调度器和数据流
公开(公告)号：US20090175275A1
公开(公告)日：2009-07-09
申请号：US12348938
申请日：2009-01-06
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

4. 发明授权

US07466715B2 Flexible control block format for frame description and management 失效
标题翻译：灵活的控制块格式，用于帧描述和管理
公开(公告)号：US07466715B2
公开(公告)日：2008-12-16
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译：用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。每个单独的数据包由FCB描述和控制。与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。当帧在输入队列中时，格式不需要第三个字。

5. 发明授权

US06757795B2 Apparatus and method for efficiently sharing memory bandwidth in a network processor 失效
标题翻译：在网络处理器中有效共享存储器带宽的装置和方法
公开(公告)号：US06757795B2
公开(公告)日：2004-06-29
申请号：US10068392
申请日：2002-02-05
申请人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
发明人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
IPC分类号： G05F1200
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
摘要翻译：网络处理器（NP）包括允许最大限度利用存储器的控制器。控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。通过这样做，每个存储器访问都利用了完整的存储器带宽。

6. 发明授权

US07474672B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07474672B2
公开(公告)日：2009-01-06
申请号：US10364069
申请日：2003-02-11
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

7. 发明授权

US07643511B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07643511B2
公开(公告)日：2010-01-05
申请号：US12327761
申请日：2008-12-03
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

8. 发明授权

US07317727B2 Method and systems for controlling ATM traffic using bandwidth allocation technology 失效
标题翻译：使用带宽分配技术控制ATM流量的方法和系统
公开(公告)号：US07317727B2
公开(公告)日：2008-01-08
申请号：US10442762
申请日：2003-05-21
申请人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
发明人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
IPC分类号： H04L12/56 , G01R31/08 , H04J3/16
CPC分类号： H04L47/32 , H04L12/5602 , H04L47/2408 , H04L47/2416 , H04L47/50 , H04L47/525 , H04L47/621 , H04L2012/5631 , H04L2012/5679
摘要： A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.
摘要翻译：公开了一种在计算机系统中管理异步传输模式（ATM）流量的方法和系统。计算机系统用于发送，接收或发送和接收多个ATM流。每个ATM流具有多个ATM信元，最小ATM带宽保证和最大ATM带宽。该方法和系统包括确定ATM流是否存在过量带宽。该方法和系统还包括在超额带宽周期期间适度地增加为每个ATM流发送的ATM信元的一部分。发送的ATM信元的部分不超过最大ATM带宽限制。如果ATM流提供足够的提供负载，则在流中发送的ATM信元的部分不小于最小ATM带宽保证。

9. 发明授权

US5608876A Add-in board with enable-disable expansion ROM for PCI bus computers 失效
标题翻译：附加板与PCI总线计算机的启用禁用扩展ROM
公开(公告)号：US5608876A
公开(公告)日：1997-03-04
申请号：US447022
申请日：1995-05-22
申请人： Ariel Cohen , William G. Holland , Joseph F. Logan , Avi Parash
发明人： Ariel Cohen , William G. Holland , Joseph F. Logan , Avi Parash
IPC分类号： G06F13/36 , G06F12/06 , G06F13/14 , G06F13/00
CPC分类号： G06F12/0684
摘要： An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a `read/write` register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer. If the Expansion ROM is presented as a read/write register with non-zero values, the PCI computer concludes that an Expansion ROM exists and "shadows" its contents into the memory of the PCI computer.
摘要翻译：用于外围组件互连（PCI）计算机的适配器或附加卡包括将卡耦合到PCI总线的通用模块。该模块包括一组选择性可编程配置寄存器，它们由适配器上的微处理器加载。模块上的电路布置发出一个命令，禁止PCI处理器访问配置寄存器，直到完全加载。另一个电路装置将扩展ROM基地址寄存器作为“读/写”寄存器或只读寄存器，将所有位设置为逻辑“0”给PCI计算机。如果扩展ROM基地址寄存器被显示为所有位设置为“0”的只读寄存器，则PCI计算机得出结论，附加卡中不存在扩展ROM，并且其内容不会被遮蔽到存储器中 PCI电脑。这种禁用扩展ROM会使存储空间在计算机中保存。如果扩展ROM作为非零值的读/写寄存器显示，则PCI计算机得出结论，扩展ROM存在，并将其内容“阴影”到PCI计算机的存储器中。

10. 发明授权

US08169906B2 Controlling ATM traffic using bandwidth allocation technology 失效
标题翻译：使用带宽分配技术控制ATM流量
公开(公告)号：US08169906B2
公开(公告)日：2012-05-01
申请号：US11946057
申请日：2007-11-28
申请人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
发明人： Patrick Droz , Ilias Iliadis , Clark D. Jeffries , Andreas Kind , Joseph F. Logan
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28
CPC分类号： H04L47/32 , H04L12/5602 , H04L47/2408 , H04L47/2416 , H04L47/50 , H04L47/525 , H04L47/621 , H04L2012/5631 , H04L2012/5679
摘要： A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.
摘要翻译：公开了一种在计算机系统中管理异步传输模式（ATM）流量的方法和系统。计算机系统用于发送，接收或发送和接收多个ATM流。每个ATM流具有多个ATM信元，最小ATM带宽保证和最大ATM带宽。该方法和系统包括确定ATM流是否存在过量带宽。该方法和系统还包括在超额带宽周期期间适度地增加为每个ATM流发送的ATM信元的一部分。发送的ATM信元的部分不超过最大ATM带宽限制。如果ATM流提供足够的提供负载，则在流中发送的ATM信元的部分不小于最小ATM带宽保证。

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