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1. 发明授权

US07995472B2 Flexible network processor scheduler and data flow 失效
标题翻译：灵活的网络处理器调度器和数据流
公开(公告)号：US07995472B2
公开(公告)日：2011-08-09
申请号：US12348938
申请日：2009-01-06
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： G01R31/08 , H04L12/28 , H04L12/54
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

2. 发明授权

US07483429B2 Method and system for flexible network processor scheduler and data flow 失效
标题翻译：灵活的网络处理器调度器和数据流的方法和系统
公开(公告)号：US07483429B2
公开(公告)日：2009-01-27
申请号：US11133477
申请日：2005-05-18
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： H04L12/56 , H04J3/24 , G06F15/00
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

3. 发明申请

US20090175275A1 FLEXIBLE NETWORK PROCESSOR SCHEDULER AND DATA FLOW 失效
标题翻译：灵活的网络处理器调度器和数据流
公开(公告)号：US20090175275A1
公开(公告)日：2009-07-09
申请号：US12348938
申请日：2009-01-06
申请人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
发明人： Jean L. Calvignac , Chih-jen Chang , Joseph F. Logan , Fabrice J. Verplanken , Daniel Wind
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

4. 发明授权

US07466715B2 Flexible control block format for frame description and management 失效
标题翻译：灵活的控制块格式，用于帧描述和管理
公开(公告)号：US07466715B2
公开(公告)日：2008-12-16
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译：用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。每个单独的数据包由FCB描述和控制。与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。当帧在输入队列中时，格式不需要第三个字。

5. 发明授权

US08854996B2 Accelerating data packet parsing 有权
标题翻译：加速数据包解析
公开(公告)号：US08854996B2
公开(公告)日：2014-10-07
申请号：US13183953
申请日：2011-07-15
申请人： Francois Abel , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Fabrice J. Verplanken
发明人： Francois Abel , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Fabrice J. Verplanken
IPC分类号： H04L12/801 , H04L12/741 , G06F9/38
CPC分类号： G06F9/3885 , H04L45/74 , H04L47/10
摘要： Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
摘要翻译：为包括解析器的网络处理器提供机制，该解析器可操作以在正常操作模式或重复操作模式下工作，解析器处于正常操作模式中，分别在第一和第二工作循环中执行至少一个规则，在重复操作模式中的解析器可操作以重复执行重复指令，执行对应于一个工作循环的每个重复。

6. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

7. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

8. 发明授权

US07715428B2 Multicore communication processing 有权
标题翻译：多核通讯处理
公开(公告)号：US07715428B2
公开(公告)日：2010-05-11
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/66 , H04J3/16 , H04J3/22
CPC分类号： H04L47/50
摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了用于处理数据处理设备之间的通信的机制。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

9. 发明授权

US07277982B2 DRAM access command queuing structure 有权
标题翻译： DRAM访问命令排队结构
公开(公告)号：US07277982B2
公开(公告)日：2007-10-02
申请号：US10899937
申请日：2004-07-27
申请人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译：访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。仲裁器首先将DRAM访问划分为写访问和读访问。访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。基于写入队列状态，写入接收数据包在存储体之间旋转。每个存储体的写入队列的状态也可以用于系统流控制。仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

10. 发明授权

US09088594B2 Providing to a parser and processors in a network processor access to an external coprocessor 有权
标题翻译：向网络处理器中的解析器和处理器提供对外部协处理器的访问
公开(公告)号：US09088594B2
公开(公告)日：2015-07-21
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/30 , H04L29/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

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