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1. 发明授权

US06586326B2 Metal planarization system 失效
公开(公告)号：US06586326B2
公开(公告)日：2003-07-01
申请号：US09804783
申请日：2001-03-13
申请人： Jayanthi Pallinti , Samuel V. Dunton , Ronald J. Nagahara
发明人： Jayanthi Pallinti , Samuel V. Dunton , Ronald J. Nagahara
IPC分类号： H01L2100
CPC分类号： H01L21/288 , H01L21/7684
摘要： A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material. The eroded portion of the metallic element is thereby restored. By removing precursor material from those areas in which no replacement with the desired material is wanted, the desired material is selectively deposited only in those place where the precursor material remains, and where it is desired to fill in the cavities or dishing that was created in the areas of the softer metallic elements between the harder laterally surrounding elements during a prior chemical mechanical polishing process. Thus, the microelectronic device is more fully planarized, as the dishing is filled in, and the metallic element is supplemented with an additional amount of desired material.

2. 发明授权

US06951808B2 Metal planarization system 失效
标题翻译：金属平面化系统
公开(公告)号：US06951808B2
公开(公告)日：2005-10-04
申请号：US10400278
申请日：2003-03-27
申请人： Jayanthi Pallinti , Samuel V. Dunton , Ronald J. Nagahara
发明人： Jayanthi Pallinti , Samuel V. Dunton , Ronald J. Nagahara
IPC分类号： H01L21/288 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/288 , H01L21/7684
摘要： A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material. The eroded portion of the metallic element is thereby restored. By removing precursor material from those areas in which no replacement with the desired material is wanted, the desired material is selectively deposited only in those place where the precursor material remains, and where it is desired to fill in the cavities or dishing that was created in the areas of the softer metallic elements between the harder laterally surrounding elements during a prior chemical mechanical polishing process. Thus, the microelectronic device is more fully planarized, as the dishing is filled in, and the metallic element is supplemented with an additional amount of desired material.
摘要翻译：一种用于恢复微电子器件中的金属元件的暴露的上表面空腔中的侵蚀部分的方法，其中所述金属元件具有硬度，并且所述金属元件被横向元件横向包围，其中所述侧向元件内的至少一个结构具有大于金属元件的硬度的硬度。至少在金属元件的上表面的空腔中沉积前体材料。沉积前体材料至少填充金属元件的上表面的空腔的厚度。前体材料具有小于侧向元件内的至少一种结构的硬度的硬度。前驱体材料根据需要从侧向元件移除，并且前体材料被平坦化。只有金属元件的上表面的空腔内的前体材料被选择性地替换为所需的材料。从而恢复金属元件的侵蚀部分。通过从其中不需要用期望的材料替换的那些区域中除去前体材料，所需的材料仅选择性地沉积在前体材料保留的那些位置，并且在那里需要填充在在先前的化学机械抛光过程中，较硬的横向周围元件之间的较软的金属元件的区域。因此，当填充凹陷时，微电子器件更加完全平坦化，并且金属元件补充有额外量的所需材料。

3. 发明授权

US06752916B1 Electrochemical planarization end point detection 有权
标题翻译：电化学平面终点检测
公开(公告)号：US06752916B1
公开(公告)日：2004-06-22
申请号：US10061519
申请日：2002-02-01
申请人： Yan Fang , Jayanthi Pallinti , Ronald J. Nagahara
发明人： Yan Fang , Jayanthi Pallinti , Ronald J. Nagahara
IPC分类号： C25D2112
CPC分类号： B23H5/08 , C25F3/02
摘要： A method for determining an end point of a planarization process for removing metal from a surface of a substrate submerged in an electrolytic solution or slurry. A first electrode is provided which is operable to contact the surface of the substrate, such as a working electrode of a potentiostat system. A second electrode is provided which is operable to contact the electrolytic solution, such as a reference electrode of the potentiostat system. The first electrode is contacted to the surface of the substrate and an electrochemical property is measured, such as the electrochemical potential between the first and second electrodes, where the electrochemical property is indicative of an electrochemical characteristic of the substrate-slurry system. The planarization process is preferably stopped when a substantial change in the electrochemical potential of the system is measured. By measuring the electrochemical potential between the substrate and slurry using the first and second electrodes during the planarization process, the present invention provides an accurate indication of the time at which the metal is completely removed from the surface of the substrate. Thus, implementation of the invention substantially reduces the probability of removing too much or too little material during planarization.
摘要翻译：一种确定用于从浸没在电解液或浆料中的衬底的表面去除金属的平坦化工艺的终点的方法。提供第一电极，其可操作以接触基板的表面，例如恒电位仪系统的工作电极。提供第二电极，其可操作以接触电解溶液，例如恒电位仪系统的参比电极。第一电极与衬底的表面接触，并且测量电化学性能，例如第一和第二电极之间的电化学电势，其中电化学性质表示衬底 - 浆料系统的电化学特性。当测量系统的电化学电位的实质性变化时，优选停止平坦化处理。通过在平坦化工艺期间通过使用第一和第二电极测量衬底和浆料之间的电化学电势，本发明提供了从衬底的表面完全去除金属的时间的精确指示。因此，本发明的实施基本上降低了在平坦化期间去除太多或太少材料的可能性。

4. 发明授权

US06417093B1 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing 有权
标题翻译：在平坦化之前通过在金属层上形成可平面化材料层来平坦化集成电路结构的金属填充沟槽的方法
公开(公告)号：US06417093B1
公开(公告)日：2002-07-09
申请号：US09703745
申请日：2000-10-31
申请人： James J. Xie , Ronald J. Nagahara , Jayanthi Pallinti , Akihisa Ueno
发明人： James J. Xie , Ronald J. Nagahara , Jayanthi Pallinti , Akihisa Ueno
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A process for forming an integrated circuit structure wherein trenches and/or vias are formed in a predetermined pattern in a dielectric layer, lined with a barrier layer of a first electrically conductive material, and then filled with a second electrically conductive material, and the structure is then planarized to remove the first and second electrically conductive material from the upper surface of the dielectric layer, wherein the improvements comprise: a) before the planarizing step, forming over the second electrically conductive material a layer of a planarizable material capable of being planarized at about the same rate as the first electrically conductive material; and b) then planarizing the structure to remove: i) the planarizable material; ii) the second electrically conductive material; and iii) the first electrically conductive material; above the upper surface of the dielectric material; whereby the planarizable material above the second electrically conductive material in the trenches protects the second electrically conductive material while the first electrically conductive material is being removed from the upper surface of the dielectric layer by the planarizing step to prevent erosion of the upper surface of the second electrically conductive layer.
摘要翻译：一种用于形成集成电路结构的方法，其中沟槽和/或通孔以介电层形成为预定图案，衬有第一导电材料的阻挡层，然后填充有第二导电材料，并且结构然后被平坦化以从电介质层的上表面去除第一和第二导电材料，其中改进包括：a）在平坦化步骤之前，在第二导电材料上形成能够被平坦化的可平面化材料层以与第一导电材料大致相同的速率; 然后平面化结构以移除：i）可平面化材料; ii）第二导电材料; 和ii）第一导电材料;在电介质材料的上表面之上;由此沟槽中的第二导电材料上方的可平面化材料保护第二导电材料，同时第一导电材料从第二导电材料的上表面所述介电层通过所述平坦化步骤来防止所述第二导电层的上表面的侵蚀。

5. 发明授权

US06713394B2 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures 有权
标题翻译：用于平坦化集成电路结构的方法，其抑制邻近下面的凸起结构的低介电常数介电材料的开裂
公开(公告)号：US06713394B2
公开(公告)日：2004-03-30
申请号：US10253158
申请日：2002-09-24
申请人： Ronald J. Nagahara , Jayanthi Pallinti , Dawn Michelle Lee
发明人： Ronald J. Nagahara , Jayanthi Pallinti , Dawn Michelle Lee
IPC分类号： H01L21302
CPC分类号： H01L21/31051 , H01L21/31633 , H01L21/76819
摘要： A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal of a portion of the overall volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit structure before the planarization step results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.
摘要翻译：一种集成电路结构的平面化处理，其抑制或防止低k电介质材料的破裂，该低介电材料包括在下面的集成电路结构的凸起部分上形成的一层或多层电介质材料中的一种。在平坦化步骤之前，在集成电路结构的凸起部分上形成的一个或多个介电层上形成可移除掩模。在掩模中形成开口以暴露集成电路结构的这些凸起部分中的至少一些上的该区域中的一个或多个介电层的上表面的一部分。然后通过掩模中的这种开口蚀刻下面的一个或多个电介质层的暴露部分，以减少覆盖集成电路结构的这种凸起部分的一个或多个电介质层的总量。然后去除掩模，并且该结构经受化学机械抛光步骤以使结构的上表面平坦化。在平坦化步骤之前，先前去除覆盖集成电路结构的凸起部分的区域中的一个或多个电介质层的总体积的一部分导致CMP工艺的缩短，这又导致缩短在此期间结构受到CMP工艺的机械应力的影响。这就抑制或消除了在低k电介质层的邻近集成电路结构的凸起部分附近的低k电介质层的破裂。

6. 发明授权

US06503828B1 Process for selective polishing of metal-filled trenches of integrated circuit structures 有权
标题翻译：用于选择性抛光集成电路结构的金属填充沟槽的工艺
公开(公告)号：US06503828B1
公开(公告)日：2003-01-07
申请号：US09882124
申请日：2001-06-14
申请人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
发明人： Ronald J. Nagahara , James J. Xie , Akihisa Ueno , Jayanthi Pallinti
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.
摘要翻译：本发明提供了一种通过在主导电层的凹陷区域上形成抛光阻挡层的步骤来选择性地研磨集成电路结构的主导电层的工艺; 并且抛光未被抛光阻挡层覆盖的主导电层的部分。通过本发明的方法处理的集成电路结构在介电材料层中包含一个或多个开口，并且主导电层填充一个或多个开口，使得主导电层的凹陷区域覆盖所述一个或多个更多开口

7. 发明授权

US06607967B1 Process for forming planarized isolation trench in integrated circuit structure on semiconductor substrate 有权
标题翻译：在半导体衬底上形成集成电路结构中的平面化隔离沟槽的工艺
公开(公告)号：US06607967B1
公开(公告)日：2003-08-19
申请号：US09714000
申请日：2000-11-15
申请人： Jayanthi Pallinti , Dawn M. Lee , Ronald J. Nagahara
发明人： Jayanthi Pallinti , Dawn M. Lee , Ronald J. Nagahara
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform. The planarization process include: removing portions of the filler layer over the liner layer on the upper surface of the substrate until portions of the underlying liner layer on the upper surface of the substrate are exposed; treating the exposed portions of the liner layer to inhibit removal of the exposed liner layer portions; continuing to remove the remainder of the filler layer on the liner layer over the upper surface of the substrate until all of the underlying liner layer on the upper surface of the substrate is exposed; and then removing the liner layer over the upper surface of the substrate and over the filler layer in the trenches until all of the liner layer is removed from the upper surface of the substrate; whereby removal of all of the filler layer on the liner layer over the upper surface of the substrate, while inhibiting removal of the liner layer over the upper surface of the substrate until such filler layer removal on the liner layer over the upper surface of the substrate is completed, will result in formation of a planarized surface on the upper surface of the substrate, and the upper surfaces of the filler layer and the liner layer in the trenches.
摘要翻译：公开了一种用于在用介电材料填充衬底中的隔离沟槽之后对半导体衬底进行平面化的工艺，其中介电材料的衬垫层的相应厚度沉积在衬底的上表面和沟槽中，和/或填充层沉积在衬层上以填充沟槽的介电材料毯可能不均匀。平坦化工艺包括：在衬底的上表面上的衬垫层上去除填料层的部分，直到衬底的上表面上的下层衬垫层的部分露出; 处理衬里层的暴露部分以阻止暴露的衬垫层部分的去除; 继续在衬底的上表面上去除衬垫层上的填充层的剩余部分，直到衬底的上表面上的所有下面的衬垫层露出; 然后在衬底的上表面上并在沟槽中的填料层上除去衬垫层，直到衬底的所有层从衬底的上表面去除; 从而在衬底的上表面上去除衬垫层上的所有填料层，同时抑制衬底层在衬底的上表面上的移除，直到衬底上的填料层在衬底的上表面上移除将导致在基板的上表面上形成平坦化的表面，并且在沟槽中形成填料层和衬垫层的上表面。

8. 发明授权

US06489242B1 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures 有权
标题翻译：用于平坦化集成电路结构的方法，其抑制邻近下面的凸起结构的低介电常数介电材料的开裂
公开(公告)号：US06489242B1
公开(公告)日：2002-12-03
申请号：US09661465
申请日：2000-09-13
申请人： Ronald J. Nagahara , Jayanthi Pallinti , Dawn Michelle Lee
发明人： Ronald J. Nagahara , Jayanthi Pallinti , Dawn Michelle Lee
IPC分类号： H01L21302
CPC分类号： H01L21/31051 , H01L21/31633 , H01L21/76819
摘要： A planarization process for an integrated circuit structure which inhibits or prevents cracking of low k dielectric material which comprises one of one or more layers of dielectric material formed over raised portions of the underlying integrated circuit structure. Prior to the planarization step, a removable mask is formed over such one or more dielectric layers formed over raised portions of the integrated circuit structure. Openings are formed in the mask to expose a portion of the upper surface of the one or more dielectric layers in the region over at least some of these raised portions of the integrated circuit structure. Exposed portions of the underlying one or more dielectric layers are then etched through such openings in the mask to reduce the overall amount of the one or more dielectric layers overlying such raised portions of the integrated circuit structure. The mask is then removed and the structure is subject to a chemical mechanical polishing step to planarize the upper surface of the structure. The prior removal of a portion of the overall volume of the one or more dielectric layers in the region overlying the raised portions of the integrated circuit structure before the planarization step results in a shortening of the CMP process which, in turn, results in a shortening of the time during which the structure is subject to the mechanical stresses of the CMP process. This inhibits or eliminates cracking of the low k dielectric layer adjacent the region of the low k dielectric layer over raised portions of the underlying integrated circuit structure.
摘要翻译：一种集成电路结构的平面化处理，其抑制或防止低k电介质材料的破裂，该低介电材料包括在下面的集成电路结构的凸起部分上形成的一层或多层电介质材料中的一种。在平坦化步骤之前，在集成电路结构的凸起部分上形成的一个或多个介电层上形成可移除掩模。在掩模中形成开口以暴露集成电路结构的这些凸起部分中的至少一些上的该区域中的一个或多个介电层的上表面的一部分。然后通过掩模中的这种开口蚀刻下面的一个或多个电介质层的暴露部分，以减少覆盖集成电路结构的这种凸起部分的一个或多个电介质层的总量。然后去除掩模，并且该结构经受化学机械抛光步骤以使结构的上表面平坦化。在平坦化步骤之前，先前去除覆盖集成电路结构的凸起部分的区域中的一个或多个电介质层的总体积的一部分导致CMP工艺的缩短，这又导致缩短在此期间结构受到CMP工艺的机械应力的影响。这就抑制或消除了在低k电介质层的邻近集成电路结构的凸起部分附近的低k电介质层的破裂。

9. 发明授权

US06372524B1 Method for CMP endpoint detection 有权
标题翻译： CMP端点检测方法
公开(公告)号：US06372524B1
公开(公告)日：2002-04-16
申请号：US09946895
申请日：2001-09-05
申请人： James J. Xie , Jayanthi Pallinti , Ronald J. Nagahara
发明人： James J. Xie , Jayanthi Pallinti , Ronald J. Nagahara
IPC分类号： H01L2100
CPC分类号： H01L22/26
摘要： A method for planarizing an integrated circuit on a substrate to a target surface of the substrate where at least portions of the target surface are of a first material having a first reflectivity. The substrate is overlaid with a top layer of a second material having a second reflectivity thereby forming an upper surface. Material is removed from the upper surface in a planarizing process, and the first reflectivity and second reflectivity of the upper surface are sensed with multiple wavelengths of electromagnetic radiation. The planarization process is stopped when a ratio of the second reflectivity to the first reflectivity equals a predetermined value.
摘要翻译：一种用于将基板上的集成电路平坦化到基板的目标表面的方法，其中目标表面的至少一部分是具有第一反射率的第一材料。衬底覆盖有具有第二反射率的第二材料的顶层，从而形成上表面。在平坦化处理中从上表面去除材料，并且利用多个电磁辐射波长来感测上表面的第一反射率和第二反射率。当第二反射率与第一反射率的比等于预定值时，停止平坦化处理。

10. 发明授权

US6114215A Generating non-planar topology on the surface of planar and near-planar substrates 失效
标题翻译：在平面和近平面基板的表面上产生非平面拓扑
公开(公告)号：US6114215A
公开(公告)日：2000-09-05
申请号：US111271
申请日：1998-07-06
申请人： Richard S. Osugi , Ronald J. Nagahara
发明人： Richard S. Osugi , Ronald J. Nagahara
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002
摘要： A process for modifying an alignment mark is described. The process includes: (i) fabricating the alignment mark on an integrated circuit substrate surface, which alignment mark includes an alignment mark fill material of defined composition; and (ii) introducing a step in the alignment mark by polishing the integrated circuit substrate surface and removing at least some of the alignment mark fill material from the integrated circuit substrate to form a modified alignment mark. The modified alignment mark is capable of allowing an alignment tool to detect the modified alignment mark when the modified alignment mark is covered by an opaque layer and thereby align a first layer of the integrated circuit substrate to the opaque layer that is disposed above the first layer.
摘要翻译：描述用于修改对准标记的过程。该方法包括：（i）在集成电路衬底表面上制造对准标记，该对准标记包括具有限定组成的对准标记填充材料; 以及（ii）通过研磨集成电路基板表面并从集成电路基板去除至少一些对准标记填充材料以形成修改的对准标记，在对准标记中引入步骤。当修改的对准标记被不透明层覆盖时，修改的对准标记能够允许对准工具检测修改的对准标记，从而将集成电路基板的第一层对准到设置在第一层之上的不透明层。

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