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1. 发明授权

US5583811A Transistor structure for erasable and programmable semiconductor memory devices 失效
标题翻译：用于可擦除和可编程半导体存储器件的晶体管结构
公开(公告)号：US5583811A
公开(公告)日：1996-12-10
申请号：US275016
申请日：1994-07-13
申请人： Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/04 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C16/0425 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883 , H01L27/105 , H01L27/115
摘要： A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
摘要翻译：一个可编程EEPROM单元结构，其分立栅极结构与浮置栅极和附加程序栅极之间的耦合电容器串联，以提供增强的注入效率。电子注入由源极侧的控制栅极控制。耦合电容器的面积在编程期间以对浮栅的高电压的实质耦合因子进行选择，以便在控制栅极和浮置栅极之间的沟道区域中的分裂点处产生热电子注入。因此可以实现在5V漏极电压下的微秒编程。

2. 发明授权

US6115285A Device and method for multi-level charge/storage and reading out 有权
标题翻译：用于多级充电/存储和读出的装置和方法
公开(公告)号：US6115285A
公开(公告)日：2000-09-05
申请号：US202481
申请日：1998-12-14
申请人： Donato Montanari , Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Donato Montanari , Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/02 , G11C11/56 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C2211/5631
摘要： The present invention discloses a memory device having memory cells capable of storing three or more charge leves in said memory cell. The cells can be programmed according to a method including a single pulse charge level injection mechanism in said cells. The method does not require a program verify scheme, permits increased speed during programming, and reduces the area necessary for storing one bit of information. The memory device of the present invention further includes information write or storage or programmation means, information erase means and information read-out means. Another object of the present invention is to provide a method and a circuit that implements said method for determining the charge level of a memory cell having t possible levels (t being larger than or equal to three). The circuit measures the similarity of the memory cell drain current with the drain current of each of n references, determines the one reference which is the most similar to the memory cell and thereby identifies the charge level of said memory cell.
摘要翻译： PCT No.PCT / EP97 / 00561 Sec。 371 1998年12月14日第 102（e）日期1998年12月14日PCT 1997年2月7日提交PCT公布。第WO97 / 48099号公报日期1997年12月18日本发明公开了一种具有能够在所述存储单元中存储三个或更多个充电电荷的存储单元的存储器件。可以根据包括所述单元中的单个脉冲电荷注入机制的方法对单元进行编程。该方法不需要程序验证方案，允许在编程期间增加速度，并减少存储一位信息所需的面积。本发明的存储装置还包括信息写入或存储或编程装置，信息擦除装置和信息读出装置。本发明的另一个目的是提供一种实现用于确定具有t个可能电平（t大于或等于3个）的存储单元的电荷电平的所述方法的方法和电路。电路测量存储单元漏极电流与n个参考中每一个的漏极电流的相似度，确定与存储单元最相似的一个参考，从而识别所述存储单元的电荷电平。

3. 发明授权

US5583810A Method for programming a semiconductor memory device 失效
标题翻译：半导体存储器件编程方法
公开(公告)号：US5583810A
公开(公告)日：1996-12-10
申请号：US80225
申请日：1993-06-21
申请人： Jan Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C16/04 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C16/0425 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883 , H01L27/105 , H01L27/115
摘要： A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
摘要翻译：一个可编程EEPROM单元结构，其分立栅极结构与浮置栅极和附加程序栅极之间的耦合电容器串联，以提供增强的注入效率。电子注入由源极侧的控制栅极控制。耦合电容器的面积在编程期间以对浮栅的高电压的实质耦合因子进行选择，以便在控制栅极和浮置栅极之间的沟道区域中的分裂点处产生热电子注入。因此可以实现在5V漏极电压下的微秒编程。

4. 发明授权

US06282124B1 Method of erasing a flash EEPROM memory cell array optimized for low power consumption 有权
公开(公告)号：US06282124B1
公开(公告)日：2001-08-28
申请号：US09327036
申请日：1999-06-07
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C1134
CPC分类号： G11C16/0425 , G11C5/142 , G11C16/10 , G11C16/16 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

5. 发明授权

US6009013A Contactless array configuration for semiconductor memories 失效
标题翻译：非接触阵列配置用于半导体存储器
公开(公告)号：US6009013A
公开(公告)日：1999-12-28
申请号：US426685
申请日：1995-04-21
申请人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C11/34
CPC分类号： G11C16/0425 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883 , H01L27/105 , H01L27/115
摘要： The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.
摘要翻译：本发明涉及电可擦除和可编程的非易失性半导体存储器（EEPROM）领域，特别涉及用于特定类型的存储晶体管的实际和有效实现的非接触式阵列配置。这种存储晶体管允许通过使用增强的源侧注入机制来进行快速5V的编程。该概念要求在场氧化物区域中的用于将高电压电容耦合到浮动栅极的编程门。因此，在编程期间建立了非常高的注入电流。然而，这个附加的程序门大大增加了单元区域。本公开示出了一种非接触5V的仅闪存EEPROM阵列配置，其依赖于共享程序行，以便最小化由该程序门引起的区域开销。此外，提供了具有共享字线的存储器阵列，其进一步增强了可实现的密度。

6. 发明授权

US06243293B1 Contacted cell array configuration for erasable and programmable semiconductor memories 有权
标题翻译：用于可擦除和可编程半导体存储器的接触电池阵列配置
公开(公告)号：US06243293B1
公开(公告)日：2001-06-05
申请号：US09267443
申请日：1999-03-12
申请人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C1134
CPC分类号： G11C16/0425 , G11C16/0441
摘要： A contacted array of programmable and erasable semiconductor memory devices. Each of the memory devices has a split gate structure, including a source region, a drain region, a channel extending between the source and drain regions, a floating gate extending over a portion of the channel with a first dielectric layer therebetween, a control gate extending over a portion of the floating gate through a second dielectric layer, and a program gate extending above the floating gate with a dielectric layer therebetween. The program gate forms a capacitor with the floating gate with a coupling ratio sufficient to couple a voltage at least as high as the drain voltage to the floating gate, thereby establishing a high voltage at a point in the channel between the control gate and the floating gate and ensuring a high hot-electron injection towards the floating gate.
摘要翻译：联系的可编程和可擦除半导体存储器件阵列。每个存储器件具有分离栅极结构，包括源极区域，漏极区域，在源极和漏极区域之间延伸的沟道;浮置栅极，其在沟道的一部分上延伸，其间具有第一介电层;控制栅极在浮动栅极的一部分上延伸穿过第二介电层，以及在浮置栅极之上延伸有介电层的程序栅极。程序栅极与浮置栅极形成电容器，其耦合比足以将至少与漏极电压一样高的电压耦合到浮置栅极，从而在控制栅极和浮置栅极之间的沟道中的一个点处建立高电压并且确保向浮动栅极施加高的热电子注入。

7. 发明授权

US6044015A Method of programming a flash EEPROM memory cell array optimized for low power consumption 失效
公开(公告)号：US6044015A
公开(公告)日：2000-03-28
申请号：US694812
申请日：1996-08-09
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C5/14 , G11C11/34 , G11C16/04 , G11C16/10 , G11C16/16 , H01L27/115
CPC分类号： G11C16/0425 , G11C16/10 , G11C16/16 , G11C5/142 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

8. 发明授权

US5969991A Method of erasing a flash EEPROM memory cell array optimized for low power consumption 失效
标题翻译：擦除针对低功耗优化的闪存EEPROM存储单元阵列的方法
公开(公告)号：US5969991A
公开(公告)日：1999-10-19
申请号：US867329
申请日：1997-06-02
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C5/14 , G11C11/34 , G11C16/04 , G11C16/10 , G11C16/16 , H01L27/115
CPC分类号： G11C16/0425 , G11C16/10 , G11C16/16 , G11C5/142 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention.
摘要翻译：本发明是用于编程SSI单元或所述单元阵列的方法。该方法实现了非常快的编程，同时仅消耗很少的功率，为诸如电池供电系统，页面模式编程等新型应用铺平了道路，实现了极高的数据吞吐量。该方法还允许在芯片上内部增加位线电压，以便规避与电源电压缩放相关联的效率降低。通过探索亚阈值状态下的SSI机制，发现栅极电流不再最大化的CG电压的最佳值，但是从电源消耗的能量最小化，并且编程期间的注入效率最大化。然而，在这种状态下存储器单元的编程，其中栅极电流是CG电压的非常陡峭的函数，然而仍然在几微秒内实现，同时仅消耗在纳安培范围内的非常小的电池电流。这允许阵列中的整个字线被同时编程，即使电源电压按比例缩小到3.3V或更低。这种可能性与每个仍然非常短的单元的物理编程时间相结合，实现了对于1Mbit器件的20ns /字节的有效编程时间，其对应于50Mbyte / s的最大编程传输速率。现有技术的闪存通常在编程期间显示出比本发明的情况下低2-3个数量级的传输速率，大约为20-300Kbyte / s。

9. 发明授权

US5841697A Contactless array configuration for semiconductor memories 失效
标题翻译：非接触阵列配置用于半导体存储器
公开(公告)号：US5841697A
公开(公告)日：1998-11-24
申请号：US426685
申请日：1995-04-21
申请人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Guido Groeseneken , Herman Maes
IPC分类号： G11C11/34
CPC分类号： G11C16/0425 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L29/42328 , H01L29/7881 , H01L29/7883
摘要： The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5 V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5 V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.
摘要翻译：本发明涉及电可擦除和可编程的非易失性半导体存储器（EEPROM）领域，特别涉及用于特定类型的存储晶体管的实际和有效实现的非接触式阵列配置。这种存储晶体管允许通过使用增强的源侧注入机制来快速进行5V的编程。该概念要求在场氧化物区域中的用于将高电压电容耦合到浮动栅极的编程门。因此，在编程期间建立了非常高的注入电流。然而，这个附加的程序门大大增加了单元区域。本公开示出了依靠共享程序行的非接触式5V唯一闪存EEPROM阵列配置，以便最小化由该程序门引起的区域开销。此外，提供了具有共享字线的存储器阵列，其进一步增强了可实现的密度。

10. 发明授权

US06707110B2 Layout configurable electrostatic discharge device for integrated circuits 有权
标题翻译：用于集成电路的布局可配置静电放电装置
公开(公告)号：US06707110B2
公开(公告)日：2004-03-16
申请号：US10131924
申请日：2002-04-25
申请人： Vincent De Heyn , Guido Groeseneken , Louis Vacaresse , Geert Gallopyn , Hugo Van Hove
发明人： Vincent De Heyn , Guido Groeseneken , Louis Vacaresse , Geert Gallopyn , Hugo Van Hove
IPC分类号： H01L2362
CPC分类号： H01L27/0259 , H01L29/7322 , H01L29/735
摘要： Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region. The device enables a lateral current component from the first highly n-doped region in the direction of the second highly n-doped region and a vertical current component from the first highly n-doped region via the buried layer in the direction of the second highly n-doped region. The width of the lateral overlap of the weakly p-doped region is determined in function of the predetermined ratio between the lateral current component and the vertical current component.
摘要翻译： 1.一种静电放电保护装置，包括具有基极接触的第一高p掺杂区域，具有集电极触点的第一高度n掺杂区域，具有发射极接触的第二高度n掺杂区域，并且位于第一高度p掺杂区域之间和第二高度n掺杂区域，第一高p掺杂区域和第二高度n掺杂区域被施加在弱p掺杂区域中，其具有向第一高度n掺杂区域延伸的横向重叠区域，具有宽度的横向重叠，第一高度n掺杂区域施加在弱n掺杂区域中，弱p掺杂区域和弱n掺杂区域被施加在更弱的n掺杂区域中，并且高度 n掺杂掩埋层位于较弱的n掺杂区域下方并在弱n掺杂区域的至少一部分和弱p掺杂区域的至少一部分的下方延伸。该器件能够在第二高度n掺杂区域的方向上产生来自第一高度n掺杂区域的横向电流分量，以及在第二高度n掺杂区域的方向上经由掩埋层从第一高度n掺杂区域的垂直电流分量 n掺杂区域。根据横向电流分量和垂直电流分量之间的预定比例来确定弱p掺杂区域的横向重叠的宽度。

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