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1. 发明授权

US06282124B1 Method of erasing a flash EEPROM memory cell array optimized for low power consumption 有权
公开(公告)号：US06282124B1
公开(公告)日：2001-08-28
申请号：US09327036
申请日：1999-06-07
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C1134
CPC分类号： G11C16/0425 , G11C5/142 , G11C16/10 , G11C16/16 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

2. 发明授权

US6044015A Method of programming a flash EEPROM memory cell array optimized for low power consumption 失效
公开(公告)号：US6044015A
公开(公告)日：2000-03-28
申请号：US694812
申请日：1996-08-09
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C5/14 , G11C11/34 , G11C16/04 , G11C16/10 , G11C16/16 , H01L27/115
CPC分类号： G11C16/0425 , G11C16/10 , G11C16/16 , G11C5/142 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.

3. 发明授权

US5969991A Method of erasing a flash EEPROM memory cell array optimized for low power consumption 失效
标题翻译：擦除针对低功耗优化的闪存EEPROM存储单元阵列的方法
公开(公告)号：US5969991A
公开(公告)日：1999-10-19
申请号：US867329
申请日：1997-06-02
申请人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
发明人： Jan F. Van Houdt , Luc Haspeslagh , Ludo Deferm , Guido Groeseneken , Herman Maes
IPC分类号： G11C5/14 , G11C11/34 , G11C16/04 , G11C16/10 , G11C16/16 , H01L27/115
CPC分类号： G11C16/0425 , G11C16/10 , G11C16/16 , G11C5/142 , H01L27/115
摘要： The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention.
摘要翻译：本发明是用于编程SSI单元或所述单元阵列的方法。该方法实现了非常快的编程，同时仅消耗很少的功率，为诸如电池供电系统，页面模式编程等新型应用铺平了道路，实现了极高的数据吞吐量。该方法还允许在芯片上内部增加位线电压，以便规避与电源电压缩放相关联的效率降低。通过探索亚阈值状态下的SSI机制，发现栅极电流不再最大化的CG电压的最佳值，但是从电源消耗的能量最小化，并且编程期间的注入效率最大化。然而，在这种状态下存储器单元的编程，其中栅极电流是CG电压的非常陡峭的函数，然而仍然在几微秒内实现，同时仅消耗在纳安培范围内的非常小的电池电流。这允许阵列中的整个字线被同时编程，即使电源电压按比例缩小到3.3V或更低。这种可能性与每个仍然非常短的单元的物理编程时间相结合，实现了对于1Mbit器件的20ns /字节的有效编程时间，其对应于50Mbyte / s的最大编程传输速率。现有技术的闪存通常在编程期间显示出比本发明的情况下低2-3个数量级的传输速率，大约为20-300Kbyte / s。

4. 发明授权

US6071825A Fully overlapped nitride-etch defined device and processing sequence 失效
标题翻译：完全重叠氮化物蚀刻定义的器件和处理顺序
公开(公告)号：US6071825A
公开(公告)日：2000-06-06
申请号：US984778
申请日：1997-12-04
申请人： Ludo Deferm
发明人： Ludo Deferm
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/00
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/7836
摘要： The present invention relates to methods for fabricating Fully Overlapped Nitride-Etch Defined (Fond) devices. These methods permit the lateral dimension and depth of the lowly-doped source and drain extensions to be independently controlled and well defined.
摘要翻译：本发明涉及制造全覆盖氮化物蚀刻（Fond）装置的方法。这些方法允许低掺杂源极和漏极延伸部的横向尺寸和深度被独立地控制和定义良好。

5. 发明授权

US6153484A Etching process of CoSi.sub.2 layers 失效
标题翻译： CoSi2层的蚀刻工艺
公开(公告)号：US6153484A
公开(公告)日：2000-11-28
申请号：US814973
申请日：1996-06-19
申请人： Ricardo Alves Donaton , Karen Irma Josef Maex , Rita Verbeeck , Philippe Jansen , Rita Rooyackers , Ludo Deferm , Mikhail Rodionovich Baklanov
发明人： Ricardo Alves Donaton , Karen Irma Josef Maex , Rita Verbeeck , Philippe Jansen , Rita Rooyackers , Ludo Deferm , Mikhail Rodionovich Baklanov
IPC分类号： H01L21/265 , H01L21/3213 , H01L21/336 , H01L29/10 , H01L31/108 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/3213 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L31/108 , H01L29/1083
摘要： The present invention relates to methods for controlling the etching rate of CoSi.sub.2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schottky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.
摘要翻译：本发明涉及通过调节基于HF的溶液的pH以获得所需的蚀刻速率来控制CoSi 2层的蚀刻速率的方法。可以通过向溶液中加入pH改变化学品来调节HF基溶液的pH。本发明的另一方面是使用受控蚀刻步骤制造肖特基势垒输入检测器的改进方法。还提供了一种用于减小具有小栅极长度的有源晶体管中的漏极感应势垒降低的方法。

6. 发明授权

US06380039B2 Method for forming a FET having L-shaped insulating spacers 有权
标题翻译：用于形成具有L形绝缘间隔物的FET的方法
公开(公告)号：US06380039B2
公开(公告)日：2002-04-30
申请号：US09283709
申请日：1999-04-01
申请人： Goncal Badenes , Ludo Deferm , Stephan Beckx , Serge Vanhaelemeersch
发明人： Goncal Badenes , Ludo Deferm , Stephan Beckx , Serge Vanhaelemeersch
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L29/6659
摘要： A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.
摘要翻译：公开了一种可扩展的装置概念，特别是其制造方法，其通过使用具有浅结的低电阻率源极/漏极延伸区域允许最小的良好控制的栅极重叠。通过使用使用L形间隔物获得的这种浅结，栅极重叠不再取决于源极/漏极接触区域的结深度。特别地，L形间隔件用于局部地减小衬底中源极/漏极注入的穿透深度。这个概念对于沟道长度低于0.25μm的FET是特别有意义的，因为这种方法扩大了源极/漏极接触区域的硅化处理的工艺窗口。此外，扩展区域必须仅受限于热预算。

7. 发明授权

US06255227B1 Etching process of CoSi2 layers 有权
标题翻译： CoSi2层的蚀刻工艺
公开(公告)号：US06255227B1
公开(公告)日：2001-07-03
申请号：US09478252
申请日：2000-01-06
申请人： Ricardo Alves Donaton , Karen Irma Josef Maex , Rita Verbeeck , Philippe Jansen , Rita Rooyackers , Ludo Deferm , Mikhail Rodionovich Baklanov
发明人： Ricardo Alves Donaton , Karen Irma Josef Maex , Rita Verbeeck , Philippe Jansen , Rita Rooyackers , Ludo Deferm , Mikhail Rodionovich Baklanov
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/3213 , H01L29/1083 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L31/108
摘要： The present invention relates to methods for controlling the etching rate of CoSi2 layers by adjusting the pH of an HF-based solution to obtain the desired etch rate. The pH of the HF-based solution may be adjusted by adding pH modifying chemicals to the solution. A further aspect of the invention is an improved method for manufacturing Schotky barrier infared detectors employing the controlled etching step. A method for reducing drain induced barrier lowering in an active transistor having a small gate length is also provided.
摘要翻译：本发明涉及通过调节基于HF的溶液的pH以获得所需的蚀刻速率来控制CoSi 2层的蚀刻速率的方法。可以通过向溶液中加入pH改变化学品来调节HF基溶液的pH。本发明的另一方面是使用受控蚀刻步骤制造Schotky屏障信号检测器的改进方法。还提供了一种用于减小具有小栅极长度的有源晶体管中的漏极感应势垒降低的方法。

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