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1. 发明申请

US20100332768A1 FLEXIBLE READ- AND WRITE-MONITORED AND BUFFERED MEMORY BLOCKS 审中-公开
标题翻译：灵活的读和写监视和缓冲存储块
公开(公告)号：US20100332768A1
公开(公告)日：2010-12-30
申请号：US12493162
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Vadim Bassin , Robert Y. Geva
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Vadim Bassin , Robert Y. Geva
IPC分类号： G06F12/08
CPC分类号： G06F11/362 , G06F12/0815
摘要： A computing system includes a number of threads. The computing system is configured to allow for monitoring and testing memory blocks in a cache memory to determine effects on memory blocks by various agents. The system includes a processor. The processor includes a mechanism implementing an instruction set architecture including instructions accessible by software. The instructions are configured to: set per-hardware-thread, for a first thread, memory access monitoring indicators for a plurality of memory blocks, and test whether any monitoring indicator has been reset by the action of a conflicting memory access by another agent. The processor further includes mechanism configured to: detect conflicting memory accesses by other agents to the monitored memory blocks, and upon such detection of a conflicting access, reset access monitoring indicators corresponding to memory blocks having conflicting memory accesses, and remember that at least one monitoring indicator has been so reset.
摘要翻译：计算系统包括多个线程。计算系统被配置为允许监视和测试高速缓冲存储器中的存储器块以确定各种代理对存储器块的影响。该系统包括一个处理器。处理器包括实现包括可由软件访问的指令的指令集架构的机制。所述指令被配置为：针对第一线程设置每个硬件线程，用于多个存储器块的存储器访问监视指示符，以及通过另一代理器的冲突的存储器访问的动作来测试是否已经重置了任何监视指示符。所述处理器还包括被配置为：检测由所述被监视的存储器块的其他代理的冲突的存储器访问，并且在这种检测到冲突访问时，对应于具有冲突的存储器访问的存储器块的复位访问监视指示器，并且记住至少一个监视指示灯已经重置。

2. 发明授权

US08356166B2 Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers 有权
标题翻译：通过使用模式不可知事务读写障碍来最大限度地减少无界事务内存系统中的代码重复
公开(公告)号：US08356166B2
公开(公告)日：2013-01-15
申请号：US12493168
申请日：2009-06-26
申请人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3004 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3857 , G06F9/467
摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
摘要翻译：最大限度地减少无界事务内存系统中的代码重复。一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作与未来的TM实现可能会引入未知的未来TM执行模式。

3. 发明申请

US20100332808A1 MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM 有权
标题翻译：在不必要的交易记忆系统中最小化代码重复
公开(公告)号：US20100332808A1
公开(公告)日：2010-12-30
申请号：US12493168
申请日：2009-06-26
申请人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3004 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3857 , G06F9/467
摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
摘要翻译：最大限度地减少无界事务内存系统中的代码重复。一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作与未来的TM实现可能会引入未知的未来TM执行模式。

4. 发明授权

US08489864B2 Performing escape actions in transactions 有权
标题翻译：在交易中执行逃生动作
公开(公告)号：US08489864B2
公开(公告)日：2013-07-16
申请号：US12493167
申请日：2009-06-26
申请人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
发明人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/467 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.
摘要翻译：在基于硬件的事务内存系统中执行非事务性转义操作。一种方法包括处理器上的硬件线程，开始针对线程的基于硬件的事务。所述方法还包括暂停所述基于硬件的事务并对所述线程执行非事务性的一个或多个操作，并且不受以下事务的影响：所述事务的事务监视和缓冲，所述事务的中止或者所述事务的中止提交交易。在对线程执行一个或多个操作之后，非事务性地，该方法还包括恢复事务并事务地执行附加操作。执行附加操作后，该方法还包括提交或中止事务。

5. 发明申请

US20100332807A1 PERFORMING ESCAPE ACTIONS IN TRANSACTIONS 有权
标题翻译：执行交易中的避税行为
公开(公告)号：US20100332807A1
公开(公告)日：2010-12-30
申请号：US12493167
申请日：2009-06-26
申请人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
发明人： Gad Sheaffer , Jan Gray , Martin Taillefer , Ali-Reza Adl-Tabatabai , Bratin Saha , Vadim Bassin , Robert Y. Geva , David Callahan
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/467 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.
摘要翻译：在基于硬件的事务内存系统中执行非事务性转义操作。一种方法包括处理器上的硬件线程，开始针对线程的基于硬件的事务。所述方法还包括暂停所述基于硬件的事务并对所述线程执行非事务性的一个或多个操作，并且不受以下事务的影响：所述事务的事务监视和缓冲，所述事务的中止或者所述事务的中止提交交易。在对线程执行一个或多个操作之后，非事务性地，该方法还包括恢复事务并事务地执行附加操作。执行附加操作后，该方法还包括提交或中止事务。

6. 发明授权

US08812796B2 Private memory regions and coherence optimizations 有权
标题翻译：私人记忆区域和一致性优化
公开(公告)号：US08812796B2
公开(公告)日：2014-08-19
申请号：US12493164
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/46
CPC分类号： G06F12/0835 , G06F9/467 , G06F12/0811 , G06F12/0831 , G06F2209/521
摘要： Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.
摘要翻译：专用或共享只读存储器区域。一个实施例可以在包括多个代理的计算环境中实践。一种方法包括通过使软件利用处理器级指令向硬件指定私有或共享的只读存储器地址区域来将用于声明特定代理私有的一个或多个存储器区域或仅在代理之间共享的操作。该方法包括执行处理器级别指令的代理，以指定对代理私有的一个或多个存储器区域或者在多个代理之间共享只读。作为代理执行处理器级别指令的结果，所述处理器级指令指定一个或多个存储器区域对于所述代理是专用的，或者在多个代理之间共享为只读存储器区域，硬件组件监视所述一个或多个存储器区域以进行冲突访问或防止冲突访问一个或多个存储器区域。

7. 发明申请

US20100332753A1 WAIT LOSS SYNCHRONIZATION 有权
标题翻译：等待丢失同步
公开(公告)号：US20100332753A1
公开(公告)日：2010-12-30
申请号：US12493163
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Bratin Saha
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Bratin Saha
IPC分类号： G06F12/02 , G06F1/32 , G06F12/08
CPC分类号： G06F12/0831 , G06F1/3225
摘要： Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.
摘要翻译：在内存访问监控丢失时同步线程。使用处理器级指令作为处理器，读取或写入监视器的指令集体系结构的一部分而被包括，以分别从第一组一个或多个存储器位置和读取的或其他存储器位置的其他代理检测写入或读取或写入设置在第二组一个或多个不同存储单元上的写监视器。执行处理器级指令，这使得处理器暂停执行指令，并且可选地进入低功率模式，等待丢失第一或第二组一个或多个存储器位置的读或写监视器。在一个或多个存储器位置的第一或第二组上检测到冲突的访问，或者检测到超时。结果，该方法包括恢复指令的执行。

8. 发明申请

US20100332771A1 PRIVATE MEMORY REGIONS AND COHERENCE OPTIMIZATIONS 有权
标题翻译：私人存储区域和协调优化
公开(公告)号：US20100332771A1
公开(公告)日：2010-12-30
申请号：US12493164
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F9/467 , G06F12/0811 , G06F12/0831 , G06F2209/521
摘要： Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.
摘要翻译：专用或共享只读存储器区域。一个实施例可以在包括多个代理的计算环境中实践。一种方法包括通过使软件利用处理器级指令向硬件指定私有或共享的只读存储器地址区域来将用于声明特定代理私有的一个或多个存储器区域或仅在代理之间共享的操作。该方法包括执行处理器级别指令的代理，以指定对代理私有的一个或多个存储器区域或者在多个代理之间共享只读。作为代理执行处理器级别指令的结果，所述处理器级指令指定一个或多个存储器区域对于所述代理是专用的，或者在多个代理之间共享为只读存储器区域，硬件组件监视所述一个或多个存储器区域以进行冲突访问或防止冲突访问一个或多个存储器区域。

9. 发明授权

US08161247B2 Wait loss synchronization 有权
标题翻译：等待丢失同步
公开(公告)号：US08161247B2
公开(公告)日：2012-04-17
申请号：US12493163
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Bratin Saha
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Bratin Saha
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/00 , G06F1/26 , G06F1/32 , G06F9/46
CPC分类号： G06F12/0831 , G06F1/3225
摘要： Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locations and a read, or write monitor on a second set of one or more different memory locations are set. A processor level instruction is executed, which causes the processor to suspend executing instructions and optionally to enter a low power mode pending loss of a read or write monitor for the first or second set of one or more memory locations. A conflicting access is detected on the first or second set of one or more memory locations or a timeout is detected. As a result, the method includes resuming execution of instructions.
摘要翻译：在内存访问监控丢失时同步线程。使用处理器级指令作为处理器，读取或写入监视器的指令集体系结构的一部分而被包括，以分别从第一组一个或多个存储器位置和读取的或其他存储器位置的其他代理检测写入或读取或写入设置在第二组一个或多个不同存储单元上的写监视器。执行处理器级指令，这使得处理器暂停执行指令，并且可选地进入低功率模式，等待丢失第一或第二组一个或多个存储器位置的读或写监视器。在一个或多个存储器位置的第一或第二组上检测到冲突的访问，或者检测到超时。结果，该方法包括恢复指令的执行。

10. 发明申请

US20100332721A1 OPERATING SYSTEM VIRTUAL MEMORY MANAGEMENT FOR HARDWARE TRANSACTIONAL MEMORY 有权
标题翻译：操作系统硬件事务存储器虚拟内存管理
公开(公告)号：US20100332721A1
公开(公告)日：2010-12-30
申请号：US12493161
申请日：2009-06-26
申请人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
发明人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
IPC分类号： G06F12/08
CPC分类号： G06F12/1045 , G06F12/0815
摘要： Operating system virtual memory management for hardware transactional memory. A method may be performed in a computing environment where an application running on a first hardware thread has been in a hardware transaction, with transactional memory hardware state in cache entries correlated by memory hardware when data is read from or written to data cache entries. The data cache entries are correlated to physical addresses in a first physical page mapped from a first virtual page in a virtual memory page table. The method includes an operating system deciding to unmap the first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
摘要翻译：硬件事务内存的操作系统虚拟内存管理。可以在运行在第一硬件线程上的应用程序已经处于硬件事务中的计算环境中执行一种方法，当数据从数据高速缓存条目读取或写入数据高速缓存条目时，高速缓存条目中的事务性存储器硬件状态由存储器硬件相关联。数据高速缓存条目与从虚拟存储器页表中的第一虚拟页面映射的第一物理页面中的物理地址相关联。该方法包括决定取消映射第一虚拟页面的操作系统。结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。实施例可以进一步挂起内核模式下的硬件事务。实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

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