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1. 发明授权

US4791314A Oscillation-free, short-circuit protection circuit 失效
标题翻译：无振荡，短路保护电路
公开(公告)号：US4791314A
公开(公告)日：1988-12-13
申请号：US930593
申请日：1986-11-13
申请人： James R. Kuo , Timothy G. Moran
发明人： James R. Kuo , Timothy G. Moran
IPC分类号： H03K19/0175 , H03F1/52 , H03K17/08 , H03K17/082 , H03K19/003 , H03K19/013 , H03K19/018 , H03K5/153 , H03K3/295 , H03K17/14 , H03K17/30
CPC分类号： H03K19/01806 , H03F1/52 , H03K17/0826 , H03K19/0133 , H03K2017/0806
摘要： A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.
摘要翻译：能够高速运转的线路驱动电路。输出晶体管，连接到输出端子的发射极，具有连接到其基极的特殊反馈电容器。反馈电容器有助于将输出端子拉高，以提高线路驱动电路的开关速度。采用特殊的电流注入和去除技术来加速PNP电流晶体管的开关时间。线路驱动器电路还具有特殊的电路，用于限制输出电流超过一定限度并保持线路驱动电路不会过热。

2. 发明授权

US4791313A Bipolar transistor switching enhancement circuit 失效
标题翻译：双极晶体管开关增强电路
公开(公告)号：US4791313A
公开(公告)日：1988-12-13
申请号：US930608
申请日：1986-11-13
申请人： James R. Kuo , Brian R. Carey , Timothy G. Moran
发明人： James R. Kuo , Brian R. Carey , Timothy G. Moran
IPC分类号： H03K5/02 , H03K19/003 , H03K19/013 , H03K19/018 , H03K19/082 , H04L25/02 , H03K5/01 , H03K17/04
CPC分类号： H03K19/00307 , H03K19/0133 , H03K19/01831 , H03K19/0826 , H03K5/02
摘要： A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

3. 发明授权

US6157180A Power supply regulator circuit for voltage-controlled oscillator 有权
标题翻译：用于压控振荡器的电源调节器电路
公开(公告)号：US6157180A
公开(公告)日：2000-12-05
申请号：US262391
申请日：1999-03-04
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： G05F3/24 , G05F3/26 , G05F1/40 , G05F3/20
CPC分类号： G05F3/242 , G05F3/262
摘要： A power supply regulator circuit with increased rejection of variations and noise in power supply voltage which is particularly well suited to isolating a voltage-controlled oscillator (VCO) from such power supply variations and noise. The regulator circuit uses an operational amplifier connected as a voltage follower circuit to buffer the reference voltage provided as the regulated supply potential for the VCO. This buffered voltage is also used to establish the bias voltage across a current mirror circuit which is powered by the unregulated power supply and through which the supply current for the VCO flows. This circuit topography requires no compensation capacitance and, therefore, provides increased rejection of variations and noise in the power supply voltage.
摘要翻译：电源调节器电路具有增加的电源电压变化和噪声抑制特性，特别适用于将压控振荡器（VCO）与这种电源变化和噪声隔离。调节器电路使用连接作为电压跟随器电路的运算放大器来缓冲作为VCO调节电源电压提供的参考电压。该缓冲电压还用于建立跨越电流镜电路的偏压，该偏置电压由未调节的电源供电，并且VCO的电源电流通过该偏置电压流动。该电路形状不需要补偿电容，因此提供对电源电压中的变化和噪声的增加的抑制。

4. 发明授权

US5883531A Universal serial bus driver having MOS transistor gate capacitor 失效
标题翻译：具有MOS晶体管栅极电容器的通用串行总线驱动器
公开(公告)号：US5883531A
公开(公告)日：1999-03-16
申请号：US912436
申请日：1997-08-18
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03K19/0185 , H03K19/017 , H03K17/04
CPC分类号： H03K19/018585
摘要： A driver which includes an output node and an output transistor connected between the output node and a first voltage reference node. A CMOS inverter is connected to a gate of the output transistor and includes a first p-channel transistor and a first n-channel transistor that have their gates connected together. A capacitance transistor is connected to the output node and the CMOS inverter and is configured to create a capacitance therebetween. A shifting transistor has its drain-source conducting path connected in series with a drain of the first p-channel transistor and a drain of the first n-channel transistor and is configured to maintain the capacitance transistor in accumulation mode. A method of driving a line includes the steps of creating a capacitance between the output node and the CMOS inverter with a capacitance transistor having its source and drain connected together, and maintaining the capacitance transistor in accumulation mode with a shifting transistor having its drain-source conducting path connected in series with a drain of the first p-channel transistor and a drain of the first n-channel transistor of the CMOS inverter.
摘要翻译：驱动器，其包括连接在输出节点和第一电压参考节点之间的输出节点和输出晶体管。 CMOS反相器连接到输出晶体管的栅极，并且包括其栅极连接在一起的第一p沟道晶体管和第一n沟道晶体管。电容晶体管连接到输出节点和CMOS反相器，并被配置为在它们之间产生电容。移动晶体管的漏极 - 源极传导路径与第一p沟道晶体管的漏极和第一n沟道晶体管的漏极串联连接，并且被配置为将电容晶体管保持在累积模式。一种驱动线路的方法包括以下步骤：在其源极和漏极连接在一起的电容晶体管之间在输出节点和CMOS反相器之间产生电容，并且通过具有其漏源的移位晶体管将电容晶体管保持在累积模式导电路径与第一p沟道晶体管的漏极和CMOS反相器的第一n沟道晶体管的漏极串联连接。

5. 发明授权

US5701102A High-speed transmission line receiver with wide range of common mode compensation 失效
标题翻译：高速传输线接收器具有广泛的共模补偿
公开(公告)号：US5701102A
公开(公告)日：1997-12-23
申请号：US567359
申请日：1995-11-29
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03F3/45
CPC分类号： H03F3/45708 , H03F3/45475 , H03F2203/45574
摘要： A high-speed transmission line receiver includes a basic differential amplifier stage along with a gain enhancement stage, which is generally similar to the differential amplifier stage. One of the current mirror transistors in the gain enhancement stage is connected to one of the current mirror transistors in the basic amplifier stage in such a way that the magnitude of the differential current at the output of the basic amplifier stage is increased, thereby increasing the gain of the receiver without increasing its output capacitance or the time constant of the output signal. Preferably, the transistors in the gain enhancement stage are larger than the transistors in the basic amplifier stage. Increasing the gain of the line receiver reduces the distortion which may occur as a result of the failure of the line receiver to reach a clamping voltage as the common mode of the differential input signal is increased.
摘要翻译：高速传输线接收机包括基本差分放大器级以及增益增强级，其通常类似于差分放大器级。增益增强级中的电流镜晶体管中的一个以基本放大器级的输出端上的差分电流的大小增加的方式连接到基本放大器级中的电流镜晶体管之一，从而增加接收机的增益不增加其输出电容或输出信号的时间常数。优选地，增益增强级中的晶体管大于基本放大器级中的晶体管。增加线路接收机的增益可减少由于差分输入信号的共模增加而导致线路接收机故障到达钳位电压时可能发生的失真。

6. 发明授权

US5463331A Programmable slew rate CMOS buffer and transmission line driver with temperature compensation 失效
标题翻译：可编程压摆率CMOS缓冲器和带温度补偿的传输线驱动器
公开(公告)号：US5463331A
公开(公告)日：1995-10-31
申请号：US384358
申请日：1995-02-02
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： G06F13/40 , H03K19/0185
CPC分类号： G06F13/4077
摘要： A driver for providing binary signals from a data system to a transmission line is disclosed. The driver includes a first field-effect transistor (FET) coupled between an output node and ground for conducting current from the output node to ground. The output node is connectable to the transmission line. An initial charging stage provides an initial charging current to the gate of the first FET for a period of time not to exceed an initial charging time period. The initial charging time period has a length approximately equal to a period of time necessary to increase the gate voltage of the first FET from ground to the threshold voltage of the first FET. A main charging stage provides a main charging current to the gate of the first FET for a period of time not to exceed a main charging time period. A discharging stage provides a discharging current from the gate of the first FET to ground. Finally, a temperature compensation circuit is coupled to the initial charging stage, the main charging stage, and the discharging stage for adjusting the level of the initial charging current, the main charging current, and the discharging current to compensate for variations in temperature and for controlling the length of the main charging time period.
摘要翻译：公开了一种用于从数据系统向传输线提供二进制信号的驱动器。驱动器包括耦合在输出节点和地之间的第一场效应晶体管（FET），用于将电流从输出节点传导到地。输出节点可连接到传输线。初始充电阶段将初始充电电流提供给第一FET的栅极一段不超过初始充电时间段的时间。初始充电时间段具有大约等于将第一FET的栅极电压从地电位增加到第一FET的阈值电压所需的时间段。主充电级将主充电电流提供给第一FET的栅极一段不超过主充电时间段的时间。放电级提供从第一FET的栅极到地的放电电流。最后，温度补偿电路耦合到初始充电阶段，主充电阶段和放电阶段，用于调节初始充电电流，主充电电流和放电电流的电平以补偿温度变化，并且控制主充电时间段的长度。

7. 发明授权

US06411146B1 Power-off protection circuit for an LVDS driver 有权
标题翻译：用于LVDS驱动程序的断电保护电路
公开(公告)号：US06411146B1
公开(公告)日：2002-06-25
申请号：US09741938
申请日：2000-12-20
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03K302
CPC分类号： H04L25/0272 , H03K19/00315 , H04L25/028 , H04L25/0292
摘要： A power-off protection circuit for an LVDS line-driver eliminates initialization problems in a local LVDS driver circuit that are caused by a remote LVDS river when the local LVDS driver is disabled. The remote LVDS driver may introduce a signal into the substrate of the local LVDS driver when the local LVDS driver is in a power-off mode. A current source in the local LVDS driver couples power from a local power supply node to the local LVDS driver when power is active. A method and protection circuit connects the substrate of the current source to the local power supply when power is active, and decouples the substrate from the local power supply when power is deactivated. The remote LVDS driver cannot cause a false power supply signal in the local LVDS driver since the conduction path is disconnected. A first switching element couples a floating substrate node in the current source to the local power supply when the power is active. A second switching element couples the floating substrate node to a bias line when power is deactivated. The first switching element is deactivated by a rising potential in the floating substrate when the local power supply is in a power-off mode. The rising potential is caused by a signal that is transmitted by the remote LVDS driver. By isolating the floating substrate from the local power, supply, false signals are eliminated and initialization problems are avoided.
摘要翻译：用于LVDS线路驱动器的断电保护电路消除了当本地LVDS驱动器被禁用时由远程LVDS河引起的本地LVDS驱动器电路中的初始化问题。当本地LVDS驱动器处于断电模式时，远程LVDS驱动器可以将信号引入本地LVDS驱动器的基板。本地LVDS驱动器中的电流源将电源从本地电源节点耦合到本地LVDS驱动器。一种方法和保护电路在电源有效时将电流源的基板连接到本地电源，并且在断电时将基板与本地电源分离。远程LVDS驱动器不会导致本地LVDS驱动器中的虚假电源信号，因为导通路径断开。当功率有效时，第一开关元件将电流源中的浮动衬底节点耦合到本地电源。当停电时，第二开关元件将浮动衬底节点耦合到偏置线。当本地电源处于断电模式时，第一开关元件由浮置衬底中的上升电位去激活。上升电位是由远程LVDS驱动器传输的信号引起的。通过将浮动衬底与局部电源隔离，电源，消除假信号并避免初始化问题。

8. 发明授权

US5801565A High speed differential data latch 失效
标题翻译：高速差分数据锁存
公开(公告)号：US5801565A
公开(公告)日：1998-09-01
申请号：US612100
申请日：1996-03-07
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03K3/356 , H03K3/289
CPC分类号： H03K3/356121
摘要： A high speed differential data latch includes identical master and slave flip-flops. The master flip-flop is driven by a differential input data signal while both flip-flops are driven by a shared differential clock signal. Each flip-flop includes: one differential amplifier for sequentially latching the differential input data signal to provide a differential output data signal; a second differential amplifier for generating two switched supply currents from the clock signal for powering the differential data amplifier; and a third differential amplifier cross-coupled to the differential data amplifier for providing positive feedback thereto for enhancing the latching speed. The differential output data signal follows the differential input data signal during one of the differential clock states and remains latched during the other differential clock state.
摘要翻译：高速差分数据锁存器包括相同的主从触发器。主触发器由差分输入数据信号驱动，而两个触发器由共享差分时钟信号驱动。每个触发器包括：一个差分放大器，用于顺序地锁存差分输入数据信号以提供差分输出数据信号; 第二差分放大器，用于从所述时钟信号产生用于为所述差分数据放大器供电的两个开关电源电流; 以及与差分数据放大器交叉耦合的第三差分放大器，用于提供正反馈以提高锁存速度。差分输出数据信号在差分时钟状态之一期间跟随差分输入数据信号，并在其它差分时钟状态期间保持锁存。

9. 发明授权

US5646563A Charge pump with near zero offset current 失效
标题翻译：充电泵具有接近零失调电流
公开(公告)号：US5646563A
公开(公告)日：1997-07-08
申请号：US723698
申请日：1996-09-30
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03L7/089 , H03L7/06
CPC分类号： H03L7/0895
摘要： A charge pump of a phase-locked loop includes a first P channel transistor and a first N channel transistor coupled to mirror a current in a constant current source. The P channel transistor and N channel transistor are formed with dimensions that match transient responses of currents through the N and P channel transistors during switching rather than matching the gains of the N and P channel transistors. In one embodiment, the channel length of the N channel transistor is twice a channel length of the P channel transistor. A second P channel transistor and a second N channel transistor connected in series with the first P and N channel transistors switch the current through the first P channel transistor and the first N channel transistor respectively. The second P channel transistor and the second N channel transistor have matched gate-drain capacitances so that they have the same switching speed. A first capacitor coupled between the gate of the first P channel transistor and a supply voltage and a second capacitor coupled between the gate of the first N channel transistor and a reference voltage reduce the effect that jitter in the supply and reference voltages has on the charge pump.
摘要翻译：锁相环的电荷泵包括第一P沟道晶体管和第一N沟道晶体管，其被耦合以镜像恒流源中的电流。 P沟道晶体管和N沟道晶体管形成为具有与在开关期间通过N沟道晶体管和P沟道晶体管的电流的瞬态响应相匹配的尺寸，而不是匹配N沟道晶体管和P沟道晶体管的增益。在一个实施例中，N沟道晶体管的沟道长度是P沟道晶体管的沟道长度的两倍。与第一P和N沟道晶体管串联连接的第二P沟道晶体管和第二N沟道晶体管分别切换电流通过第一P沟道晶体管和第一N沟道晶体管。第二P沟道晶体管和第二N沟道晶体管具有匹配的栅极 - 漏极电容，使得它们具有相同的切换速度。耦合在第一P沟道晶体管的栅极和电源电压之间的第一电容器和耦合在第一N沟道晶体管的栅极和参考电压之间的第二电容器降低了电源和参考电压中的抖动对电荷的影响泵。

10. 发明授权

US5519728A High-speed low-voltage differential swing transmission line transceiver 失效
标题翻译：高速低压差动摆线传输线收发器
公开(公告)号：US5519728A
公开(公告)日：1996-05-21
申请号：US395744
申请日：1995-02-28
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03K19/003 , H03K5/151 , H03K17/041 , H03K17/687 , H03K19/0175 , H04L25/02 , H04B3/00 , H04L25/00
CPC分类号： H04L25/0292 , H03K17/04106 , H03K17/6871 , H03K17/6872 , H03K5/151 , H04L25/028 , H04L25/0272
摘要： A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The transistors have unequal emitter areas, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair. Since in CMOS technology current varies inversely with temperature, the current through the mirror transistor provides temperature compensation for selected components of the transceiver.
摘要翻译：数据收发器包括连接在数据传输线一端的发射机和连接在数据传输线另一端的接收机。在CMOS中形成收发器的至少一些部分。温度补偿电路连接到收发器的选定部件，以校正通过这些部件的电流的温度引起的变化。温度补偿电路包括分别连接在并行导通路径中的一对晶体管。晶体管具有不等的发射极区域，并且它们的栅极被连接在一起。通过较大晶体管的电流随着温度而直接变化，并且该电流反映在连接到晶体管对的短路栅极的电流镜晶体管中。由于在CMOS技术中，电流与温度成反比，所以通过反射镜晶体管的电流为收发器的选定部件提供了温度补偿。

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