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1. 发明授权

US08493251B2 Self-calibrated DAC with reduced glitch mapping 有权
标题翻译：自校准DAC具有减少的毛刺映射
公开(公告)号：US08493251B2
公开(公告)日：2013-07-23
申请号：US13192950
申请日：2011-07-28
申请人： James J. Riches
发明人： James J. Riches
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/0651 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog converter (DAC) is disclosed. According to some embodiments of the present disclosure, a DAC may include a plurality of current-steering elements, wherein each respective current-steering element is configured to operate as instructed by a respective calibration signal during respective steps in a calibration cycle, and at least one current-steering element is configured to operate as instructed by a first control signal during at least a first step in which the at least one current-steering element is not being calibrated, and operate as instructed by a second control signal during at least a second step in which the at least one current-steering element is not being calibrated.
摘要翻译：公开了一种数模转换器（DAC）。根据本公开的一些实施例，DAC可以包括多个电流导引元件，其中每个相应的电流导引元件被配置为在校准周期的相应步骤期间按照相应校准信号的指示进行操作，并且至少一个电流导引元件被配置为在至少一个电流导引元件未被校准的至少第一步骤期间按照第一控制信号的指示进行操作，并且在至少一个电流导引元件的至少一个所述至少一个电流导向元件未被校准的第二步骤。

2. 发明申请

US20080165041A1 CLOCK JITTER MINIMIZATION IN A CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：连续时间的时钟抖动最小化SIGMA DELTA模拟数字转换器
公开(公告)号：US20080165041A1
公开(公告)日：2008-07-10
申请号：US11621844
申请日：2007-01-10
申请人： John J. Parkes , James G. Mittel , James J. Riches
发明人： John J. Parkes , James G. Mittel , James J. Riches
IPC分类号： H03M1/12 , H03M3/02
CPC分类号： H03M3/372 , H03M3/424
摘要： A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
摘要翻译：适用于连续时间Σ-Δ模数转换器中的反馈转换器的数 - 模转换器。数模转换器具有离散时间数字信号输入，接受与第一数据时钟信号和离散时钟发生器的断言同步的数字信号采样，该离散时钟发生器响应于接收到第一数据信号的断言而产生输出脉冲数据时钟。输出脉冲被断言固定持续时间，与第一个数据时钟的抖动无关。数模转换器还包括连续时间模拟输出，其在断言输出脉冲期间产生具有对应于数字信号采样的幅度的连续时间模拟输出信号。

3. 发明授权

US07937058B2 Controlling the bandwidth of an analog filter 有权
标题翻译：控制模拟滤波器的带宽
公开(公告)号：US07937058B2
公开(公告)日：2011-05-03
申请号：US11550534
申请日：2006-10-18
申请人： Mahibur Rahman , John J. Parkes, Jr. , James J. Riches
发明人： Mahibur Rahman , John J. Parkes, Jr. , James J. Riches
IPC分类号： H04B1/10
CPC分类号： H04B1/30 , H03H11/1256 , H03H11/1291 , H03H2210/012 , H03H2210/015 , H03H2210/025 , H03H2210/036
摘要： A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.
摘要翻译：用于改变模拟滤波器（132）的截止频率的数字调谐系统（250）包括数字合成器（292和294），用于产生应用于滤波器的输入的双色调校信号（196）过滤器增加。滤波器包括至少一个R / C电路，其具有用于改变用于改变截止频率的电容器的品质因数和阵列（308和310）的两个电阻器（304和306）。滤波器对每个音调（405和407）的幅度响应（409和411）的幅度通过两个离散的傅里叶变换单频率二次谐波频域功率检测电路（253和254）来测量，而滤波器通过多个的电容设置。对于每个电容设置，通过将滤波器的响应与每个音调的差值与预选值进行比较来选择R / C电路的最佳电容。

4. 发明授权

US07397291B1 Clock jitter minimization in a continuous time sigma delta analog-to-digital converter 有权
标题翻译：连续时间Σ-Δ模数转换器中的时钟抖动最小化
公开(公告)号：US07397291B1
公开(公告)日：2008-07-08
申请号：US11621844
申请日：2007-01-10
申请人： John J. Parkes, Jr. , James G. Mittel , James J. Riches
发明人： John J. Parkes, Jr. , James G. Mittel , James J. Riches
IPC分类号： H03K3/70 , H03K3/023 , H03M1/66
CPC分类号： H03M3/372 , H03M3/424
摘要： A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
摘要翻译：适用于连续时间Σ-Δ模数转换器中的反馈转换器的数 - 模转换器。数模转换器具有离散时间数字信号输入，接受与第一数据时钟信号和离散时钟发生器的断言同步的数字信号采样，该离散时钟发生器响应于接收到第一数据信号的断言而产生输出脉冲数据时钟。输出脉冲被断言固定持续时间，与第一个数据时钟的抖动无关。数模转换器还包括连续时间模拟输出，其在断言输出脉冲期间产生具有对应于数字信号采样的幅度的连续时间模拟输出信号。

5. 发明授权

US06864817B1 Signaling dependent adaptive analog-to-digital converter (ADC) system and method of using same 失效
标题翻译：信号依赖自适应模数转换器（ADC）系统及其使用方法
公开(公告)号：US06864817B1
公开(公告)日：2005-03-08
申请号：US10748543
申请日：2003-12-30
申请人： Raul Salvi , John J. Parkes, Jr. , James J. Riches
发明人： Raul Salvi , John J. Parkes, Jr. , James J. Riches
IPC分类号： H03M1/12 , H03M3/00 , H04B1/06
CPC分类号： H03M3/49 , H03M3/424 , H03M3/486
摘要： An adaptive analog-to-digital converter (ADC) system (100) includes an automatic gain control (AGC) controller (101) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) (103) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (105). The ADC (105) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller (101).
摘要翻译：自适应模数转换器（ADC）系统（100）包括自动增益控制（AGC）控制器（101），用于从射频（RF）接收器接收带内和带外信号，并产生 AGC控制信号。数字信号处理器（DSP）（103）然后用于解释AGC控制信号并向ADC（105）提供调整信号。 ADC（105）使用调整信号通过基于接收到的RF信号和呈现给AGC控制器（101）的所需协议要求来调整位分辨率，参考电容和偏置来动态地控制ADC系统100的效率。

6. 发明申请

US20130027235A1 Self-Calibrated DAC with Reduced Glitch Mapping 有权
标题翻译：自校准DAC具有减少的毛刺映射
公开(公告)号：US20130027235A1
公开(公告)日：2013-01-31
申请号：US13192950
申请日：2011-07-28
申请人： James J. Riches
发明人： James J. Riches
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/0651 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog converter (DAC) is disclosed. According to some embodiments of the present disclosure, a DAC may include a plurality of current-steering elements, wherein each respective current-steering element is configured to operate as instructed by a respective calibration signal during respective steps in a calibration cycle, and at least one current-steering element is configured to operate as instructed by a first control signal during at least a first step in which the at least one current-steering element is not being calibrated, and operate as instructed by a second control signal during at least a second step in which the at least one current-steering element is not being calibrated.
摘要翻译：公开了一种数模转换器（DAC）。根据本公开的一些实施例，DAC可以包括多个电流导引元件，其中每个相应的电流导引元件被配置为在校准周期的相应步骤期间按照相应校准信号的指示进行操作，并且至少一个电流导引元件被配置为在至少一个电流导引元件未被校准的至少第一步骤期间按照第一控制信号的指示进行操作，并且在至少一个电流导引元件的至少一个所述至少一个电流导向元件未被校准的第二步骤。

7. 发明申请

US20080096514A1 CONTROLLING THE BANDWIDTH OF AN ANALOG FILTER 有权
标题翻译：控制模拟滤波器的带宽
公开(公告)号：US20080096514A1
公开(公告)日：2008-04-24
申请号：US11550534
申请日：2006-10-18
申请人： Mahibur Rahman , John J. Parkes , James J. Riches
发明人： Mahibur Rahman , John J. Parkes , James J. Riches
IPC分类号： H04B1/06 , H04B1/10
CPC分类号： H04B1/30 , H03H11/1256 , H03H11/1291 , H03H2210/012 , H03H2210/015 , H03H2210/025 , H03H2210/036
摘要： A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.
摘要翻译：用于改变模拟滤波器（132）的截止频率的数字调谐系统（250）包括数字合成器（292和294），用于产生应用于滤波器的输入的双色调校信号（196）过滤器增加。滤波器包括至少一个R / C电路，其具有用于改变用于改变截止频率的电容器的品质因数和阵列（308和310）的两个电阻器（304和306）。滤波器对每个音调（405和407）的幅度响应（409和411）的幅度通过两个离散的傅里叶变换单频率二次谐波频域功率检测电路（253和254）来测量，而滤波器通过多个的电容设置。对于每个电容设置，通过将滤波器的响应与每个音调的差值与预选值进行比较来选择R / C电路的最佳电容。

8. 发明授权

US06937089B2 Offset, delay and parasitically immune resister-capacitor (RC) tracking loop and method of using same 有权
标题翻译：偏移，延迟和寄生电阻电阻（RC）跟踪循环及其使用方法
公开(公告)号：US06937089B2
公开(公告)日：2005-08-30
申请号：US10748878
申请日：2003-12-30
申请人： James J. Riches
发明人： James J. Riches
IPC分类号： H03B1/00 , H03H7/01 , H03K5/00
CPC分类号： H03H7/0153
摘要： A resistor capacitor (RC) tracking loop includes a parasitic insensitive integrator (211) charged by a buffer (207) with offset compensation. The integrator (211) operates to provide an accurate ramped voltage proportional to a measured RC time constant. A single comparator (213) is used for sensing the voltage ramp rate by detecting two multiplexed reference voltages (VREFLO VREFHI). A timer within controller (201) is triggered by the VREFLO crossing at comparator (213). The timer counts the number of precision reference clock periods (FREF) that occur between the VREFLO and VREFHI crossings and adjusts an accumulator within controller (201) to a value (M). This value (M) is directly used to adjust a resistor and/or capacitor array used in a continuous time filter whose bandwidth and corner frequency can be precisely tuned.
摘要翻译：电阻电容器（RC）跟踪环路包括由具有偏移补偿的缓冲器（207）充电的寄生不敏感积分器（211）。积分器（211）操作以提供与测量的RC时间常数成正比的准确的斜坡电压。单个比较器（213）用于通过检测两个多路复用的参考电压（V REF REF REF REF）来感测电压斜坡率。控制器（201）内的定时器在比较器（213）处由V REF REF 交叉触发。定时器计数出现在V REF REF 和V 交叉点之间的精确参考时钟周期数（F SUB> REF ），并调整一个累加器控制器（201）到值（M）。该值（M）直接用于调整连续时间滤波器中使用的电阻和/或电容阵列，其带宽和转角频率可被精确调谐。

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