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    • 1. 发明申请
    • CLOCK JITTER MINIMIZATION IN A CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER
    • 连续时间的时钟抖动最小化SIGMA DELTA模拟数字转换器
    • US20080165041A1
    • 2008-07-10
    • US11621844
    • 2007-01-10
    • John J. ParkesJames G. MittelJames J. Riches
    • John J. ParkesJames G. MittelJames J. Riches
    • H03M1/12H03M3/02
    • H03M3/372H03M3/424
    • A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.
    • 适用于连续时间Σ-Δ模数转换器中的反馈转换器的数 - 模转换器。 数模转换器具有离散时间数字信号输入,接受与第一数据时钟信号和离散时钟发生器的断言同步的数字信号采样,该离散时钟发生器响应于接收到第一数据信号的断言而产生输出脉冲 数据时钟。 输出脉冲被断言固定持续时间,与第一个数据时钟的抖动无关。 数模转换器还包括连续时间模拟输出,其在断言输出脉冲期间产生具有对应于数字信号采样的幅度的连续时间模拟输出信号。
    • 2. 发明申请
    • CONTROLLING THE BANDWIDTH OF AN ANALOG FILTER
    • 控制模拟滤波器的带宽
    • US20080096514A1
    • 2008-04-24
    • US11550534
    • 2006-10-18
    • Mahibur RahmanJohn J. ParkesJames J. Riches
    • Mahibur RahmanJohn J. ParkesJames J. Riches
    • H04B1/06H04B1/10
    • H04B1/30H03H11/1256H03H11/1291H03H2210/012H03H2210/015H03H2210/025H03H2210/036
    • A digital tuning system (250) for changing a cutoff frequency of an analog filter (132) includes digital synthesizers (292 and 294) for producing a two-tone calibration signal (196) applied to an input of the filter after a quality factor of the filter is increased. The filter includes at least one R/C circuit with two resistors (304 and 306) for changing the quality factor and arrays (308 and 310) of capacitors for changing the cutoff frequency. The amplitude of the magnitude responses (409 and 411) of the filter to each tone (405 and 407) is measured by a two discrete Fourier transform single-frequency bin power detection circuits (253 and 254) while the filter is sequenced through a plurality of capacitance settings. An optimal capacitance for the R/C circuit is selected by comparing, to a pre-selected value, a difference between the responses of the filter to each tone, for each capacitance setting.
    • 用于改变模拟滤波器(132)的截止频率的数字调谐系统(250)包括数字合成器(292和294),用于产生应用于滤波器的输入的双色调校信号(196) 过滤器增加。 滤波器包括至少一个R / C电路,其具有用于改变用于改变截止频率的电容器的品质因数和阵列(308和310)的两个电阻器(304和306)。 滤波器对每个音调(405和407)的幅度响应(409和411)的幅度通过两个离散的傅里叶变换单频率二次谐波频域功率检测电路(253和254)来测量,而滤波器通过多个 的电容设置。 对于每个电容设置,通过将滤波器的响应与每个音调的差值与预选值进行比较来选择R / C电路的最佳电容。
    • 3. 发明申请
    • LOAD INDEPENDENT VOLTAGE REGULATOR
    • 负载独立电压调节器
    • US20080231243A1
    • 2008-09-25
    • US11690596
    • 2007-03-23
    • Kai ZhongJohn J. Parkes
    • Kai ZhongJohn J. Parkes
    • G05F1/10
    • G05F1/56
    • An integrated circuit package (202) includes a voltage regulator (208) and a power-out pin (236) for coupling to a load circuit (210) via a connection (234) external to the integrated circuit package and for coupling to an output (230) of the voltage regulator via a connection (224, 228, 226 and 231) internal to the integrated circuit package. The internal connection has a series resistance that causes a voltage drop due to a load current. The voltage regulator compensates for the voltage drop in the internal connection using a current feedback circuit, in which the current fed back is proportional to the voltage drop caused by the series resistance of the internal connection.
    • 集成电路封装(202)包括电压调节器(208)和电源输出引脚(236),用于经由集成电路封装外部的连接(234)耦合到负载电路(210),并用于耦合到输出 (230),经由集成电路封装内部的连接(224,228,226和231)。 内部连接具有由负载电流引起的电压降的串联电阻。 电压调节器使用电流反馈电路补偿内部连接中的电压降,其中反馈的电流与由内部连接的串联电阻引起的电压降成比例。
    • 6. 发明授权
    • High capacitance drive fast slewing amplifier
    • 高电容驱动快速回转放大器
    • US06297676B1
    • 2001-10-02
    • US09692985
    • 2000-10-23
    • John W. SimmonsJohn J. ParkesManbir Nag
    • John W. SimmonsJohn J. ParkesManbir Nag
    • H03B100
    • H03K17/167
    • A ring inhibiting charging and discharging circuit (100) for use with an amplification circuit (102) that drives a load (108) is responsive to an input (104) and is capable of generating an output (106) corresponding to the input (104). The ring inhibiting charging and discharging circuit (100) includes a charge element (120) that is responsive to the output (112) from the amplification circuit (102). The charge element (120) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (130) is responsive to the output (106) from the amplification circuit (102) and includes a feedback circuit (132) and a staging circuit (134). The feedback circuit (132) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage. The staging circuit (134) is responsive to difference signal and gradually reduces the rate at which the load (108) is discharged over a preselected period of time once the difference signal indicates that the output voltage is within a preselected range of the input voltage.
    • 用于与驱动负载(108)的放大电路(102)一起使用的环形抑制充电和放电电路(100)响应于输入(104)并且能够产生对应于输入(104)的输出(106) )。 禁止充电和放电电路(100)包括响应于来自放大电路(102)的输出(112)的电荷元件(120)。 当输入电压大于输出电压的预选倍数时,充电元件(120)能够对负载充电。 放电电路(130)响应来自放大电路(102)的输出(106)并且包括反馈电路(132)和分级电路(134)。 当输出电压小于输入电压的预选倍数时,反馈电路(132)断言差分信号。 一旦差分信号表示输出电压在输入电压的预选范围内,分级电路(134)响应差分信号并逐渐降低负载(108)在预选时间段内放电的速率。