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    • 10. 发明申请
    • ELECTRIC CIRCUIT FOR GENERATING A PERIODIC SIGNAL
    • 电路,用于生成周期信号
    • WO02025815A1
    • 2002-03-28
    • PCT/EP2001/009828
    • 2001-08-24
    • H03K3/0231H03K4/501H03K3/70
    • H03K3/0231H03K4/501
    • The invention relates to an electric circuit for generating a periodic signal (CLK) comprising: a capacitor device (C), which has a first terminal (K1) and a second terminal (K2); a signal node (K3) that is connected, via a first switching device (S1), to the first terminal (K1) and, via a second switching device (S2), to the second terminal (K2), to which a first signal (Vc) having a first period (T/2) is applied; a discharging device (STS) that is connected, via a third switching device (S3), to the first terminal (K1) and, via a fourth switching device (S4), to the second terminal (K2), whereby the second terminal (K2), via a fifth switching device (S5), and the first terminal (K1), via a sixth switching device (S6), are connected to a first reference potential (Vm); and comprising a clock pulse generating device (KOMP; STUP; TH; CG) for receiving the first signal (Vc) and for generating a first switch clock pulse ( PHI 1), a second switch clock pulse ( PHI 2), and the periodic signal (CLK). The first and the second switch clock pulse ( PHI 1; PHI 2) do not overlap and are inverse with regard to one another. The first, third and fifth switch device (S1; S3; S5) can be controlled by the first switch clock pulse ( PHI 1), and the second, fourth and sixth switch device (S2; S4; S6) can be controlled by the second switch clock pulse ( PHI 2). The first and second switch clock pulse ( PHI 1; PHI 2) and the periodic signal (CLK) have a second period (T), which is an even multiple of the first period (T/2).
    • 本发明提供了用于产生具有电容器装置的周期信号(CLK)(C),具有第一端子(K1)和第二端子(K2)包括电路; 通过第一开关装置(S1)向所述第一终端(K1),并且通过第二开关装置(S2)到所述第二端子(K2)被连接的信号节点(K3)中,向其中的第一信号具有第一(Vc)的 抵接时期的持续时间(T / 2); 被连接到排出装置(STS),其通过第3开关装置(S3)到所述第一端子(K1),并通过第四开关装置(S4)到所述第二端子(K2); 其中,所述第二端子(K2)通过第五开关装置(S5)与第一端子(K1)通过第六开关元件(S6)到第一参考电位(V)连接; 和时钟产生装置(COMP; STUP; TH; CG),用于接收所述第一信号(VC)和用于产生第一开关时钟(PHI 1),第二开关时钟(PHI 2)和周期信号(CLK)。 第一和第二开关时钟(PHI 1,PHI 2)是不重叠的,并反比于彼此。 所述第一,第三和第五开关装置(S1; S3; S5)(; S4; S6 S2)由所述第二开关时钟(PHI 2)可以控制由第一开关时钟(PHI 1)和所述第二,第四和第六开关装置相连。 第一和第二开关时钟(PHI 1,PHI 2)和周期信号(CLK)具有第二周期的持续时间(T),它是一个偶数倍所述第一周期的持续时间(T / 2)的。