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1. 发明授权

US3983479A Electrical defect monitor structure 失效
标题翻译：电气缺陷监测结构
公开(公告)号：US3983479A
公开(公告)日：1976-09-28
申请号：US598480
申请日：1975-07-23
申请人： James H. Lee , Akella V. S. Satya , Ashwin K. Ghatalia , Donald R. Thomas
发明人： James H. Lee , Akella V. S. Satya , Ashwin K. Ghatalia , Donald R. Thomas
IPC分类号： G01R31/02 , G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04 , G01R31/26
CPC分类号： G01R31/2853
摘要： A semiconductor defect monitoring structure employs a series of electrically testable serpentine stripe patterns having different widths and spacing in order to determine the distribution of the density of defects by size. Metal stripe patterns are superposed and rotated 90.degree. with respect to diffusion stripe patterns in a semiconductor wafer. A set of four field effect transistor devices are connected to each stripe pattern in such a way that tests may be made for all defects without interference between adjacent patterns. The defect monitoring structure helps to determine defects such as opens in diffusion and metallization, shorts in metallization, shorts in diffusion, pinholes in a thin oxide, and pinholes in a thick oxide.
摘要翻译：半导体缺陷监测结构采用一系列具有不同宽度和间距的电可测蛇形条纹图案，以便按尺寸确定缺陷密度的分布。金属条纹图案相对于半导体晶片中的扩散条纹重叠并旋转90度。一组四个场效应晶体管器件以这样的方式连接到每个条纹图案，即可以对所有缺陷进行测试，而不会在相邻图案之间产生干涉。缺陷监测结构有助于确定诸如扩散和金属化中的开放，金属化中的短路，扩散短路，薄氧化物中的针孔以及厚氧化物中的针孔等缺陷。

2. 发明授权

US06576923B2 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06576923B2
公开(公告)日：2003-06-10
申请号：US10178329
申请日：2002-06-21
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/888 , Y10S977/89 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

3. 发明授权

US4100486A Monitor for semiconductor diffusion operations 失效
标题翻译：监控半导体扩散操作
公开(公告)号：US4100486A
公开(公告)日：1978-07-11
申请号：US776691
申请日：1977-03-11
申请人： Barry N. Casowitz , Michael D. Cowan , Charles B. Humphreys , Akella V. S. Satya
发明人： Barry N. Casowitz , Michael D. Cowan , Charles B. Humphreys , Akella V. S. Satya
IPC分类号： G01R31/26 , G01R31/28 , H01L21/22 , H01L21/66 , G01R27/02
CPC分类号： G01R31/2853 , G01R31/2637 , G01R31/2644 , G01R31/2831 , H01L22/14
摘要： An electrical defect density monitor for semiconductor device fabrication utilizing a silicide of a formed transitional metal (such as platinum silicide) on a surface of a silicon substrate as a resistor in parallel with the resistance of the underlying substrate, including diffused regions, to improve measurement sensitivity of high sheet resistivity areas. The measurement can be employed for measuring the integrity of diffused regions and/or of dielectric coatings.
摘要翻译：一种用于半导体器件制造的电缺陷密度监测器，其利用硅衬底的表面上形成的过渡金属（例如硅化铂）的硅化物作为电阻器，与包括扩散区域在内的衬底的电阻平行，以改善测量高电阻率区域的敏感性。该测量可用于测量扩散区域和/或电介质涂层的完整性。

4. 发明授权

US07655482B2 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07655482B2
公开(公告)日：2010-02-02
申请号：US11621512
申请日：2007-01-09
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

5. 发明授权

US06528818B1 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06528818B1
公开(公告)日：2003-03-04
申请号：US09648380
申请日：2000-08-25
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

6. 发明授权

US06509197B1 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06509197B1
公开(公告)日：2003-01-21
申请号：US09648212
申请日：2000-08-25
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2100
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

7. 发明授权

US07656170B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的多方向扫描
公开(公告)号：US07656170B2
公开(公告)日：2010-02-02
申请号：US11675013
申请日：2007-02-14
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Padma A. Satya, legal representative , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01R31/02
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
摘要翻译：公开了一种检查样品的方法。用至少一个粒子束沿第一方向扫描样品。用至少一个粒子束在第二个方向上扫描样品。第二方向与第一方向成一个角度。作为第一扫描的结果，发现样品的每个区域的缺陷数，并且从第二次扫描确定发现的一个或多个缺陷的位置。在具体实施例中，样本包括其上具有多个测试元件的测试结构。测试元件的第一部分在第一次扫描期间暴露于光束以识别具有缺陷的测试元件，并且第二部分测试元件在第二次扫描期间暴露以分离和表征缺陷。

8. 发明授权

US07179661B1 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07179661B1
公开(公告)日：2007-02-20
申请号：US09648095
申请日：2000-08-25
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L22/34
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

9. 发明授权

US06867606B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
公开(公告)号：US06867606B2
公开(公告)日：2005-03-15
申请号：US10390502
申请日：2003-03-13
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01N23/04 , G01Q30/16 , G01Q60/44 , G01R31/28 , G01R31/307 , H01L23/544 , G01R31/304
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01N23/04 , G01R31/2884 , G01R31/307 , H01J2237/2817 , Y10S977/849
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

10. 发明授权

US06633174B1 Stepper type test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：步进式测试结构和半导体集成电路检测方法
公开(公告)号：US06633174B1
公开(公告)日：2003-10-14
申请号：US09648093
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
IPC分类号： G01R31305
CPC分类号： G01R31/307 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , H01J2237/2817 , H01L22/12 , H01L22/34 , Y10S977/85 , Y10S977/86 , Y10S977/881
摘要： Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.
摘要翻译：公开了一种检查样品的方法。该方法包括移动到与第一组测试结构相关联的第一字段。第一组测试结构部分在第一个领域内。该方法还包括扫描第一场以确定在第一组测试结构内是否存在任何缺陷。当确定在第一组测试结构内存在缺陷时，该方法还包括重复地步进到区域并扫描这些区域，以便确定第一组测试结构内的特定缺陷位置。还公开了用于执行该方法的合适的测试结构。

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