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    • 10. 发明授权
    • Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices
    • 用于分析半导体器件上测试结构的缺陷信息的多像素方法和装置
    • US06771806B1
    • 2004-08-03
    • US09648381
    • 2000-08-25
    • Akella V. S. SatyaDavid L. AdlerBin-Ming Benjamin TsaiDavid J. Walker
    • Akella V. S. SatyaDavid L. AdlerBin-Ming Benjamin TsaiDavid J. Walker
    • G06K900
    • H01L22/34G01N21/66G01N21/9501G01N21/956G01R31/2884G01R31/307
    • Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.
    • 公开了一种用于检测半导体管芯的测试结构上的电缺陷的方法。 测试结构包括多个电隔离测试结构和多个非电隔离测试结构。 测试结构各自具有部分位于扫描区域内的部分。 扫描区域内的测试结构部分被扫描,以获得测试结构部分的电压对比度图像。 在多像素处理器中,分析获得的电压对比图像,以确定测试结构内是否存在缺陷。 在优选实施例中,多像素处理器以约25nm至200nm的范围内的像素分辨率尺寸进行操作。 在另一方面,处理器以标称等于测试结构线宽度的两倍的像素大小进行操作,以在最佳信噪比灵敏度下最大化吞吐量。 还公开了一种具有用于执行上述方法的编程指令的计算机可读介质。