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1. 发明授权

US5793698A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5793698A
公开(公告)日：1998-08-11
申请号：US844799
申请日：1997-04-22
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C7/14 , G11C8/06 , G11C8/18 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/065 , G11C7/14 , G11C8/06 , G11C8/18
摘要： The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.
摘要翻译：通过保持先前锁存的地址信号直到接收到新的地址信号之后的预定的延迟来改善地址转换检测电路。

2. 发明授权

US5608687A Output driver control for ROM and RAM devices 失效
标题翻译： ROM和RAM设备的输出驱动控制
公开(公告)号：US5608687A
公开(公告)日：1997-03-04
申请号：US563212
申请日：1995-11-27
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C16/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/409 , H03K17/04 , H03K17/16 , H03K19/0175 , G11C13/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.
摘要翻译：本发明是用于控制与具有地址转换检测电路的存储器的数据输出端耦合的中断驱动器的控制电路。存储器可在待机和主动存储器模式下在顺序存储器周期中操作。该控制电路包括一个输出使能锁存电路，该电路在前一个存储周期内提供存储器是处于待机还是工作模式的内部存储器信号，以及一个数据锁存电路，提供一个新的读取周期是否开始的内部存储器信号在记忆中当存储器内发生地址检测时，数据锁存电路复位。逻辑电路将指示存储器读取周期的数据锁存电路的输出与输出使能锁存电路的输出相结合，其指示先前存储器周期是待机还是活动。逻辑电路产生一个输出使能信号OE，它耦合到存储器的输出驱动器，以控制输出驱动器的浮点。结果，从旧数据到新数据的平滑过渡被获得，并且消除了从待机到主动模式的转换中的系统数据总线争用。

3. 发明授权

US5487038A Method for read cycle interrupts in a dynamic read-only memory 失效
标题翻译：在动态只读存储器中进行读周期中断的方法
公开(公告)号：US5487038A
公开(公告)日：1996-01-23
申请号：US290549
申请日：1994-08-15
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C16/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/409 , H03K17/04 , H03K17/16 , H03K19/0175 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.
摘要翻译：本发明是用于读周期中断的动态ROM设计。改进的存储器的时钟方案产生初始启动时钟。提供高电平时START的相对较长的脉冲时间来设置锁存器。该脉冲持续时间由PCOK或OWDN单触发电路控制。当读取周期早期发生地址中断时，当PCOK或OWDN时钟为低电平，而START为高电平时，这些单触发电路提供了重新启动循环的简单方法，通过继续循环的预充电阶段，对大多数存储器中的辅助时钟。只有与新地址输入相关的时钟才能通过早期中断来实现。这导致更少的功耗和更少的总线噪声。

4. 发明授权

US5414663A VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines 失效
标题翻译：具有改进的读出放大器的VLSI存储器，具有用于对可寻址位线进行建模的虚拟位线
公开(公告)号：US5414663A
公开(公告)日：1995-05-09
申请号：US71892
申请日：1993-06-03
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C8/06 , G11C8/10 , G11C17/12 , H01L27/115 , H03K3/3565 , G11C7/00
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/106 , G11C8/06 , G11C8/10 , H01L27/115 , H03K3/3565 , G11C2207/108
摘要： The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential sense output. Leakage currents and voltages common to both the dummy bit lines and selected bit line are thus cancelled out.Sense amplifiers incorporating this advantage may also be used in combination with a dynamic latch which is selectively disconnected from the memory array at all times other than during a memory cycle to avoid noise interference.Dummy word lines used in combination with dummy predecoder and decoder are used to make on-chip determinations of the transition points when an address signal is valid and complete. The actual initiation of the addressing of the memory may then be triggered according to a modeled transition point within each memory circuit.The worst ON state and OFF state voltages on dummy bit lines are used in a trigger circuit to generate a trigger signal for use in sense amplifiers which will reliably indicate when a valid sense decision can be made taking into consideration the individual process parameters and operating conditions of the actual memory circuit.
摘要翻译：通过提供对应于存储器单元的导通状态和截止状态的虚拟位线来改善VLSI存储器中的读出放大器的操作，对虚拟位线上的电压进行平均，并将该平均值与位线电压进行比较以产生差分输出。因此，泄漏电流和虚位线和所选位线的公共电压被抵消。结合这个优点的感应放大器也可以与动态锁存器组合使用，动态锁存器除了在存储器周期期间除了在存储器周期内有选择地与存储器阵列断开以避免噪声干扰之外。与虚拟预解码器和解码器结合使用的虚拟字线用于在地址信号有效和完成时对转换点进行片上确定。然后可以根据每个存储器电路内的建模转换点来触发存储器的寻址的实际启动。在虚拟位线上的最差的ON状态和OFF状态电压被用在触发电路中以产生用于读出放大器的触发信号，该触发信号可以在考虑到各个工艺参数和操作条件的情况下可靠地指示何时可以进行有效的感测判定的实际存储电路。

5. 发明授权

US5581203A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5581203A
公开(公告)日：1996-12-03
申请号：US435151
申请日：1995-05-05
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C8/06 , G11C8/10 , G11C17/12 , H01L27/115 , H03K3/3565 , H03H11/16
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/106 , G11C8/06 , G11C8/10 , H01L27/115 , H03K3/3565 , G11C2207/108
摘要： The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.
摘要翻译：通过对存储器中使用的各种电路和方法的改进，改进了大规模集成READ ONLY MEMORY电路的性能。根据存储器电路中的工艺温度和电压变化是否使得变化敏感组件在发生这种变化时将变慢时，由用于输出缓冲器的偏置电路产生适当的偏置电平。否则当处理温度和电压变化使得它们不影响敏感电路部分的电路速度时，偏置电路将产生适合于输出缓冲器电路内快速操作的偏置信号。通过在存储器周期期间禁用电荷泵送动作来改善从存储器周期异步操作的背偏置发生器。

6. 发明授权

US5650979A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5650979A
公开(公告)日：1997-07-22
申请号：US706721
申请日：1996-09-06
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C7/10 , G11C7/14 , G11C8/06 , G11C17/12 , G11C7/00
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/065 , G11C7/1051 , G11C7/14 , G11C8/06
摘要： The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.
摘要翻译：通过在存储器中使用的各种电路和方法中的许多不同的改进，改进了非常大规模的集成READ ONLY MEMORY电路的性能。其中一项改进涉及控制电路对输出缓冲器的控制。输出缓冲器的输出使能信号由控制电路选择性地禁止，该控制电路确定存储器周期何时实际完成。仅在存储器周期实际完成之后，传统的芯片使能信号CE耦合到输出缓冲器中的使能输入。

7. 发明授权

US6002618A NMOS input receiver circuit 失效
标题翻译： NMOS输入接收电路
公开(公告)号：US6002618A
公开(公告)日：1999-12-14
申请号：US190040
申请日：1998-11-11
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.
摘要翻译：只读存储器中的输入接收器电路具有控制滞后的反馈。第二级和附加输出被添加到接收器。只读存储器内部的开关电路噪声由添加状态和输出隔离，不能反馈到接收器电路以影响TTL电压电平的检测。使用宽和长的FET尺寸可最大限度地减少输入接收器开关电平中的制造相关变化。

8. 发明授权

US5870346A VLSI memory circuit 失效
标题翻译： VLSI存储电路
公开(公告)号：US5870346A
公开(公告)日：1999-02-09
申请号：US927773
申请日：1997-09-11
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C16/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/409 , H03K17/04 , H03K17/16 , H03K19/0175 , G11C7/00 , G11C17/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.
摘要翻译：提供存储器预充电电压VPC，其根据测量的程度跟踪高压电源VDD的变化，其维持预充电电压，尽管瞬态负载可能倾向于将预充电电压降低，并且维持预充电电压尽管在断电状态期间预充电发生器基本上被关闭。然后，预充电电压VPC用作对其产生的电路的控制输入信号和用于驱动耦合到ROM核中的位线的小上拉电流FET的内部控制电压MLC。产生内部控制信号MLC以跟踪存储器芯内的位线中的放电电流，以跟踪VPC，并且即使在断电状态下MLC电流基本上截止时也保持在其工作电压电平。

9. 发明授权

US5596544A Very large scale integrated planar read only memory 失效
标题翻译：非常大规模的集成平面只读存储器
公开(公告)号：US5596544A
公开(公告)日：1997-01-21
申请号：US426037
申请日：1995-04-21
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Jack L. Minney
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Jack L. Minney
IPC分类号： G11C17/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C16/06 , G11C17/12 , G11C17/18 , H01L21/8246 , H01L27/112 , H01L27/115 , H03K3/3565 , G11C8/00
CPC分类号： G11C7/1057 , G11C17/12 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , H01L27/115 , H03K3/3565 , G11C2207/108 , G11C7/04
摘要： Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.
摘要翻译：在存储器中操作地址锁存电路的条件是首先接收仅在数据输出驱动器切换时产生的接地浪涌控制逻辑信号SURG。这可以防止来自这些相同驱动程序的噪声错误地寻址存储器。通过选择构成锁存器的门的触发点来防止转移性，使得在输入或中间电路已经稳定之前不产生输出，并且当在几乎同时的输入之间的冲突发生时，在输入或中间电路中提供有利的输出条件。锁存器输出到其输入端的反馈进一步降低了亚稳态。

10. 发明授权

US5459693A Very large scale integrated planar read only memory 失效
标题翻译：非常大规模的集成平面只读存储器
公开(公告)号：US5459693A
公开(公告)日：1995-10-17
申请号：US16811
申请日：1993-02-11
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Jack L. Minney
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Jack L. Minney
IPC分类号： G11C17/00 , G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C16/06 , G11C17/12 , G11C17/18 , H01L21/8246 , H01L27/112 , H01L27/115 , H03K3/3565
CPC分类号： G11C7/1057 , G11C17/12 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , H01L27/115 , H03K3/3565 , G11C2207/108 , G11C7/04
摘要： In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The cascaded differential amplifiers have trigger points set by varying the channel widths of the input FETs to the CMOS differential amplifiers, or by adjusting the gains of the CMOS differential amplifiers to match the trigger point of the CMOS inverter coupled to its output. The trigger circuit is powered down to zero power dissipation whenever it is inactive.
摘要翻译：在只读存储器内核中，通过使用直接互连并直接耦合到CMOS反相器的一对级联CMOS差分放大器来实现触发信号TRIG的改进的产生，触发信号TRIG由此产生触发信号TRIG，。级联差分放大器通过改变输入FET到CMOS差分放大器的通道宽度，或者通过调整CMOS差分放大器的增益来匹配耦合到其输出端的CMOS反相器的触发点来设置触发点。触发电路无功时，功耗为零。

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