专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5793698A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5793698A
公开(公告)日：1998-08-11
申请号：US844799
申请日：1997-04-22
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C7/14 , G11C8/06 , G11C8/18 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/065 , G11C7/14 , G11C8/06 , G11C8/18
摘要： The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.
摘要翻译：通过保持先前锁存的地址信号直到接收到新的地址信号之后的预定的延迟来改善地址转换检测电路。

2. 发明授权

US5608687A Output driver control for ROM and RAM devices 失效
标题翻译： ROM和RAM设备的输出驱动控制
公开(公告)号：US5608687A
公开(公告)日：1997-03-04
申请号：US563212
申请日：1995-11-27
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C16/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/409 , H03K17/04 , H03K17/16 , H03K19/0175 , G11C13/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.
摘要翻译：本发明是用于控制与具有地址转换检测电路的存储器的数据输出端耦合的中断驱动器的控制电路。存储器可在待机和主动存储器模式下在顺序存储器周期中操作。该控制电路包括一个输出使能锁存电路，该电路在前一个存储周期内提供存储器是处于待机还是工作模式的内部存储器信号，以及一个数据锁存电路，提供一个新的读取周期是否开始的内部存储器信号在记忆中当存储器内发生地址检测时，数据锁存电路复位。逻辑电路将指示存储器读取周期的数据锁存电路的输出与输出使能锁存电路的输出相结合，其指示先前存储器周期是待机还是活动。逻辑电路产生一个输出使能信号OE，它耦合到存储器的输出驱动器，以控制输出驱动器的浮点。结果，从旧数据到新数据的平滑过渡被获得，并且消除了从待机到主动模式的转换中的系统数据总线争用。

3. 发明授权

US5487038A Method for read cycle interrupts in a dynamic read-only memory 失效
标题翻译：在动态只读存储器中进行读周期中断的方法
公开(公告)号：US5487038A
公开(公告)日：1996-01-23
申请号：US290549
申请日：1994-08-15
申请人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
发明人： James A. Komarek , Clarence W. Padgett , Scott B. Tanner , Shin-ichi Kojima , Jack L. Minney , Motohiro Oishi , Keiji Fukumura , H. Nakanishi
IPC分类号： G11C16/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18 , G11C11/407 , G11C11/409 , H03K17/04 , H03K17/16 , H03K19/0175 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.
摘要翻译：本发明是用于读周期中断的动态ROM设计。改进的存储器的时钟方案产生初始启动时钟。提供高电平时START的相对较长的脉冲时间来设置锁存器。该脉冲持续时间由PCOK或OWDN单触发电路控制。当读取周期早期发生地址中断时，当PCOK或OWDN时钟为低电平，而START为高电平时，这些单触发电路提供了重新启动循环的简单方法，通过继续循环的预充电阶段，对大多数存储器中的辅助时钟。只有与新地址输入相关的时钟才能通过早期中断来实现。这导致更少的功耗和更少的总线噪声。

4. 发明授权

US5414663A VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines 失效
标题翻译：具有改进的读出放大器的VLSI存储器，具有用于对可寻址位线进行建模的虚拟位线
公开(公告)号：US5414663A
公开(公告)日：1995-05-09
申请号：US71892
申请日：1993-06-03
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C8/06 , G11C8/10 , G11C17/12 , H01L27/115 , H03K3/3565 , G11C7/00
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/106 , G11C8/06 , G11C8/10 , H01L27/115 , H03K3/3565 , G11C2207/108
摘要： The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential sense output. Leakage currents and voltages common to both the dummy bit lines and selected bit line are thus cancelled out.Sense amplifiers incorporating this advantage may also be used in combination with a dynamic latch which is selectively disconnected from the memory array at all times other than during a memory cycle to avoid noise interference.Dummy word lines used in combination with dummy predecoder and decoder are used to make on-chip determinations of the transition points when an address signal is valid and complete. The actual initiation of the addressing of the memory may then be triggered according to a modeled transition point within each memory circuit.The worst ON state and OFF state voltages on dummy bit lines are used in a trigger circuit to generate a trigger signal for use in sense amplifiers which will reliably indicate when a valid sense decision can be made taking into consideration the individual process parameters and operating conditions of the actual memory circuit.
摘要翻译：通过提供对应于存储器单元的导通状态和截止状态的虚拟位线来改善VLSI存储器中的读出放大器的操作，对虚拟位线上的电压进行平均，并将该平均值与位线电压进行比较以产生差分输出。因此，泄漏电流和虚位线和所选位线的公共电压被抵消。结合这个优点的感应放大器也可以与动态锁存器组合使用，动态锁存器除了在存储器周期期间除了在存储器周期内有选择地与存储器阵列断开以避免噪声干扰之外。与虚拟预解码器和解码器结合使用的虚拟字线用于在地址信号有效和完成时对转换点进行片上确定。然后可以根据每个存储器电路内的建模转换点来触发存储器的寻址的实际启动。在虚拟位线上的最差的ON状态和OFF状态电压被用在触发电路中以产生用于读出放大器的触发信号，该触发信号可以在考虑到各个工艺参数和操作条件的情况下可靠地指示何时可以进行有效的感测判定的实际存储电路。

5. 发明授权

US06408008B1 Circuit for attenuation of echos caused by line variations and an interfacing system for capacitively coupling a plurality of sources to a two-wire communication line 失效
标题翻译：用于衰减由线路变化引起的回波的电路和用于将多个源电容耦合到两线通信线路的接口系统
公开(公告)号：US06408008B1
公开(公告)日：2002-06-18
申请号：US09449713
申请日：1999-11-24
申请人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
发明人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
IPC分类号： H04J302
CPC分类号： H04M19/005 , H04J3/0682 , H04L7/10 , H04L25/0266 , H04M1/723 , H04M3/005 , H04M9/003 , H04M9/005 , H04M9/02 , H04M9/025 , H04M9/027 , H04M19/04
摘要： A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.
摘要翻译：电路衰减线路变化引起的回波和无变压器，高直流阻抗，双线线路接口。为了减少回声，在与所有线路连接的所有站单元的通信线路上引入测试音。所得到的接收信号通过由处理器进行数字化和读取的峰值检测器来调节。网络的电阻和电容特性由处理器迭代，重新测量结果。该网络被设置为处理器的最小回波的最佳组合。接口系统借助于多个差分电压 - 电流放大器将多个源电容耦合到两线通信对。每个源使用差分接收放大器来从线路接收信号，并且与所述特定接口处的通信线路耦合的所有采购实体并联电阻耦合。有一个与每个源相关联的回波平衡网络。

6. 发明授权

US6018219A Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same 有权
标题翻译：家用和小型商务电话系统，用于单个内部双绞线的运行和操作方法
公开(公告)号：US6018219A
公开(公告)日：2000-01-25
申请号：US339774
申请日：1999-06-24
申请人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
发明人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
IPC分类号： H04M1/723 , H04M9/02 , G05F1/00
CPC分类号： H05B33/083 , H04M1/723 , H04M9/02
摘要： A small and economically fabricated CMOS voltage controlled crystal oscillator is provided by coupling three inverter amplifiers in series with a regenerative crystal controlled feedback loop. The first and second CMOS inverters have output nodes whose impedances are modified by a CMOS impedance modulating circuit. Also coupled to each of these two output nodes is a CMOS transistor shunt capacitor. The impedance of the output node is modified according to the magnitude of a voltage control signal applied to the CMOS modulating circuits. The self-bias of the modulating circuits is maintained substantially constant by adjusting the gate drive in each of the modulating circuits according to gate drives derived from a dummy modulating circuit. The dummy modulating circuit has as one input the voltage control signal and as its compensating gate drive, a control signal derived from a feedback loop from a dummy output node in such a manner that the self-bias of the dummy modulating circuit is maintained substantially constant. The compensating gate drive from the dummy modulating circuit is then coupled to the appropriate compensating gates within the impedance modulating circuits in the voltage controlled oscillator.
摘要翻译：通过将三个反相放大器与再生晶体控制反馈回路串联，提供了一个经济实惠的CMOS压控晶体振荡器。第一和第二CMOS反相器具有输出节点，其阻抗由CMOS阻抗调制电路修改。还耦合到这两个输出节点中的每一个是CMOS晶体管分流电容器。根据施加到CMOS调制电路的电压控制信号的大小来修改输出节点的阻抗。通过根据从虚拟调制电路得到的栅极驱动调整每个调制电路中的栅极驱动，调制电路的自偏压保持基本恒定。虚拟调制电路具有电压控制信号和作为其补偿栅极驱动的一个输入，作为从虚拟输出节点的反馈回路得到的控制信号，使得虚拟调制电路的自偏压保持基本恒定。然后将来自虚拟调制电路的补偿栅极驱动耦合到压控振荡器中的阻抗调制电路内的适当的补偿栅极。

7. 发明授权

US5650979A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5650979A
公开(公告)日：1997-07-22
申请号：US706721
申请日：1996-09-06
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C7/10 , G11C7/14 , G11C8/06 , G11C17/12 , G11C7/00
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/065 , G11C7/1051 , G11C7/14 , G11C8/06
摘要： The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.
摘要翻译：通过在存储器中使用的各种电路和方法中的许多不同的改进，改进了非常大规模的集成READ ONLY MEMORY电路的性能。其中一项改进涉及控制电路对输出缓冲器的控制。输出缓冲器的输出使能信号由控制电路选择性地禁止，该控制电路确定存储器周期何时实际完成。仅在存储器周期实际完成之后，传统的芯片使能信号CE耦合到输出缓冲器中的使能输入。

8. 发明授权

US5548592A Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same 失效
标题翻译：家用和小型商务电话系统，用于单个内部双绞线的运行和操作方法
公开(公告)号：US5548592A
公开(公告)日：1996-08-20
申请号：US435282
申请日：1995-05-05
申请人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
发明人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
IPC分类号： H04J3/06 , H04L7/10 , H04M3/00 , H04M9/00 , H04M9/02 , H04M19/00 , H04M19/04 , H04J3/02
CPC分类号： H04M9/025 , H04J3/0682 , H04L25/0266 , H04L7/10 , H04M19/005 , H04M19/04 , H04M9/005 , H04M9/02 , H04M9/027 , H04M3/005 , H04M9/003
摘要： A telephone communication system for communicating between a plurality of exterior telephone lines and a single common in-house two wire line is comprised of a control unit for coupling to the plurality of exterior telephone lines and for controlling communication between the plurality of telephone lines and the common two wire line. A plurality of station units are coupled remotely throughout the building to the common two wire line. The control unit communicates on the digital channel with the plurality of station units in a time frame subdivided into a plurality of time slots. A specified portion of each time slot is reserved for control communication between the control unit and each one of the plurality of station units. A synchronization signal is transmitted for phase locking all the station units to the control unit clock and a common frame synchronization signal is used to align all units in time. Each remote telephone or adapter box has a unique number assigned to it by the setting of a manual switch. Each number corresponds to a slot in a time frame. Thereafter all control signaling to a specific station unit occurs in a particular time slot.
摘要翻译：用于在多个外部电话线和单个公共内部双线之间通信的电话通信系统包括用于耦合到多个外部电话线并用于控制多条电话线之间的通信的控制单元和普通两条线。多个站单元在整个建筑物中远程耦合到公共两条有线线路。控制单元在被划分成多个时隙的时间帧中在数字信道上与多个站单元进行通信。每个时隙的指定部分被保留用于控制单元与多个站单元中的每一个之间的控制通信。发送同步信号用于将所有站单元锁定到控制单元时钟，并且使用公共帧同步信号来及时对齐所有单元。每个远程电话或适配器盒具有通过手动开关的设置分配给它的唯一编号。每个数字对应于时间框架中的时隙。此后，对特定站单元的所有控制信令发生在特定时隙中。

9. 发明授权

US5825777A Home and small business phone system for operation on a single internal twisted pair line and methodology for operating the same 失效
标题翻译：家用和小型商务电话系统，用于单个内部双绞线的运行和操作方法
公开(公告)号：US5825777A
公开(公告)日：1998-10-20
申请号：US669250
申请日：1996-06-21
申请人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
发明人： James A. Komarek , Jack L. Minney , Stephen P. Nordine , Harold F. Lewis , Richard Wada , John F. Stockman
IPC分类号： H04M1/723 , H04M9/02 , H04J3/02
CPC分类号： H05B33/083 , H04M1/723 , H04M9/02
摘要： The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware. Everything needed to provide a programmably customized communication and telephone network is available using only one basic chip design in the system as described above. Not only are standard telephone communications possible on a single twisted pair, but a network of telephone receivers, computers, modems, telefax devices, answering machines and any other type of information handling or communication device now known or later devised for use on a telephone line can be networked and accommodated within the system.
摘要翻译：本发明是一种能够在家庭或小型企业中常见的单个内部电话线路上操作的电话系统，其经济地在集成电路芯片内实现以提供单芯片电话，并且提供了大部分组件全功能，可靠，易于安装办公通讯系统。多频段音频网络（MAN）通过单根双绞线传输四个音频频带和数字数据频带。在同一双绞线上也提供了每秒6000位的全双工数字数据通道。每个站单元包括执行常规电话功能所需的所有控制和接口支持。这些功能包括键盘和显示器支持电路的组合，例如选通和去抖动电路，LED缓冲器，压电环驱动器，控制寄存器和通信硬件。提供可编程定制的通信和电话网络所需的一切都可以使用如上所述的系统中的一个基本芯片设计。标准电话通信不仅可以在单个双绞线上实现，而且还可以使用电话接收机，计算机，调制解调器，传真设备，应答机以及现在已知或以后设计用于电话线路的任何其他类型的信息处理或通信设备的网络可以联网和容纳在系统内。

10. 发明授权

US5581203A Semiconductor read-only VLSI memory 失效
标题翻译：半导体只读VLSI存储器
公开(公告)号：US5581203A
公开(公告)日：1996-12-03
申请号：US435151
申请日：1995-05-05
申请人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
发明人： James A. Komarek , Scott B. Tanner , Clarence W. Padgett , Jack L. Minney
IPC分类号： G11C7/06 , G11C8/06 , G11C8/10 , G11C17/12 , H01L27/115 , H03K3/3565 , H03H11/16
CPC分类号： G11C7/1057 , G11C17/126 , G11C7/062 , G11C7/065 , G11C7/106 , G11C8/06 , G11C8/10 , H01L27/115 , H03K3/3565 , G11C2207/108
摘要： The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.
摘要翻译：通过对存储器中使用的各种电路和方法的改进，改进了大规模集成READ ONLY MEMORY电路的性能。根据存储器电路中的工艺温度和电压变化是否使得变化敏感组件在发生这种变化时将变慢时，由用于输出缓冲器的偏置电路产生适当的偏置电平。否则当处理温度和电压变化使得它们不影响敏感电路部分的电路速度时，偏置电路将产生适合于输出缓冲器电路内快速操作的偏置信号。通过在存储器周期期间禁用电荷泵送动作来改善从存储器周期异步操作的背偏置发生器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式