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1. 发明授权

US08507947B2 High quality GaN high-voltage HFETS on silicon 有权
标题翻译：高品质GaN高电压HFETS硅
公开(公告)号：US08507947B2
公开(公告)日：2013-08-13
申请号：US13316305
申请日：2011-12-09
申请人： Jamal Ramdani , John P. Edwards , Linlin Liu
发明人： Jamal Ramdani , John P. Edwards , Linlin Liu
IPC分类号： H01L31/072
CPC分类号： H01L29/205 , H01L21/0226 , H01L21/02381 , H01L21/02458 , H01L21/02488 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L29/045 , H01L29/1075 , H01L29/2003 , H01L29/778 , H01L29/7786 , H01L29/78
摘要： Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al2O3 film on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the Al2O3 film. Each laminate layer includes an AlN film and a GaN film. A transistor or other device may be formed in the top GaN film.
摘要翻译：公开了适用于形成诸如异质结构场效应晶体管（HFET）的电子器件的GaN上的GaN衬底以及制造衬底的方法。形成硅晶片顶表面上的结晶Al 2 O 3膜的空隙。硅晶片的顶表面沿<111>硅晶体取向。在空隙和Al 2 O 3膜上沉积多个层压层。每个层压层包括AlN膜和GaN膜。可以在顶部GaN膜中形成晶体管或其它器件。

2. 发明申请

US20130146863A1 HIGH QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON 有权
标题翻译：硅质高品位GAN高压HFETs
公开(公告)号：US20130146863A1
公开(公告)日：2013-06-13
申请号：US13316305
申请日：2011-12-09
申请人： Jamal RAMDANI , John P. Edwards , Linlin Liu
发明人： Jamal RAMDANI , John P. Edwards , Linlin Liu
IPC分类号： H01L29/22 , H01L21/20
CPC分类号： H01L29/205 , H01L21/0226 , H01L21/02381 , H01L21/02458 , H01L21/02488 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L29/045 , H01L29/1075 , H01L29/2003 , H01L29/778 , H01L29/7786 , H01L29/78
摘要： Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline Al2O3 film on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the Al2O3 film. Each laminate layer includes an AlN film and a GaN film. A transistor or other device may be formed in the top GaN film.
摘要翻译：公开了适用于形成诸如异质结构场效应晶体管（HFET）的电子器件的GaN上的GaN衬底以及制造衬底的方法。形成硅晶片顶表面上的结晶Al 2 O 3膜的空隙。硅晶片的顶表面沿<111>硅晶体取向。在空隙和Al 2 O 3膜上沉积多个层压层。每个层压层包括AlN膜和GaN膜。可以在顶部GaN膜中形成晶体管或其它器件。

3. 发明授权

US08633094B2 GaN high voltage HFET with passivation plus gate dielectric multilayer structure 失效
标题翻译： GaN高电压HFET具有钝化加栅极电介质多层结构
公开(公告)号：US08633094B2
公开(公告)日：2014-01-21
申请号：US13373811
申请日：2011-12-01
申请人： Jamal Ramdani , Linlin Liu , John Paul Edwards
发明人： Jamal Ramdani , Linlin Liu , John Paul Edwards
IPC分类号： H01L29/778
CPC分类号： H01L29/66462 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02274 , H01L21/02315 , H01L21/0234 , H01L21/28264 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/402 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/778 , H01L29/7786 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
摘要翻译：制造用于功率晶体管器件的多层结构的方法包括在反应室内进行氮等离子体冲击，直接在氮化物基有源半导体层上形成氮化物层。然后将氮化物层的顶表面暴露于第二源。随后的氮 - 氧等离子体冲击导致氮化物层直接在氮化物层上形成。氮化物层包括钝化层，氧化氮化物层包括功率晶体管器件的栅极电介质。

4. 发明申请

US20140077266A1 Heterostructure Transistor with Multiple Gate Dielectric Layers 审中-公开
标题翻译：具有多个栅介质层的异质结晶体晶体管
公开(公告)号：US20140077266A1
公开(公告)日：2014-03-20
申请号：US13617584
申请日：2012-09-14
申请人： Jamal Ramdani , Michael Murphy , Linlin Liu
发明人： Jamal Ramdani , Michael Murphy , Linlin Liu
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L23/3192 , H01L29/2003 , H01L29/42376 , H01L29/513 , H01L29/66431 , H01L29/66462 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A first gate dielectric layer is disposed on the second active layer. A second gate dielectric layer is disposed on the first gate dielectric layer. A passivation layer is disposed over the second gate dielectric layer. A gate extends through the passivation layer to the second gate dielectric layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
摘要翻译：异质结构半导体器件包括设置在第一有源层上的第一有源层和第二有源层。在第一和第二有源层之间形成二维电子气层。第一栅介质层设置在第二有源层上。第二栅极电介质层设置在第一栅极电介质层上。钝化层设置在第二栅极电介质层上。栅极延伸穿过钝化层到第二栅极介电层。第一和第二欧姆触点电连接到第二有源层。第一和第二欧姆触点横向间隔开，栅极设置在第一和第二欧姆触点之间。

5. 发明申请

US20130140605A1 GaN high voltage HFET with passivation plus gate dielectric multilayer structure 失效
标题翻译： GaN高电压HFET具有钝化加栅极电介质多层结构
公开(公告)号：US20130140605A1
公开(公告)日：2013-06-06
申请号：US13373811
申请日：2011-12-01
申请人： Jamal Ramdani , Linlin Liu , John Paul Edwards
发明人： Jamal Ramdani , Linlin Liu , John Paul Edwards
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/66462 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02274 , H01L21/02315 , H01L21/0234 , H01L21/28264 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/402 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66431 , H01L29/778 , H01L29/7786 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.
摘要翻译：制造用于功率晶体管器件的多层结构的方法包括在反应室内进行氮等离子体冲击，直接在氮化物基有源半导体层上形成氮化物层。然后将氮化物层的顶表面暴露于第二源。随后的氮 - 氧等离子体冲击导致氮化物层直接在氮化物层上形成。氮化物层包括钝化层，氧化氮化物层包括功率晶体管器件的栅极电介质。

6. 发明申请

US20130146943A1 IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC 审中-公开
标题翻译：在国立格栅电介质和现场板电介质
公开(公告)号：US20130146943A1
公开(公告)日：2013-06-13
申请号：US13323672
申请日：2011-12-12
申请人： John P. EDWARDS , Linlin Liu
发明人： John P. EDWARDS , Linlin Liu
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/66431 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28264 , H01L29/2003 , H01L29/42376 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7786
摘要： Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode.
摘要翻译：公开了用于提供具有高质量栅极电介质和场板电介质的异质结构场效应晶体管（HFET）的方法和装置。门介质和场板介质原位沉积在半导体表面上。栅电极的位置可以通过蚀刻场板电介质中的第一图案并且使用栅极电介质作为蚀刻停止来限定。或者，可以在栅极电介质和场板电介质之间原位沉积附加的蚀刻停止层。在蚀刻第一图案之后，可以沉积导电材料并图案化以限定栅电极。电接触半导体表面的源极和漏极形成在栅电极的相对侧上。

7. 发明申请

US20100140627A1 Package for Semiconductor Devices 审中-公开
标题翻译：半导体器件封装
公开(公告)号：US20100140627A1
公开(公告)日：2010-06-10
申请号：US12575717
申请日：2009-10-08
申请人： Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
发明人： Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
IPC分类号： H01L23/495 , H01L29/20
CPC分类号： H01L23/49562 , H01L21/56 , H01L23/3107 , H01L23/562 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/2919 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要： A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.
摘要翻译：一种封装的半导体器件，包括安装在引线框的头部上的半导体管芯。多个间隔开的外部导体从集管延伸，并且至少一个外部导体在其一端具有接合线柱，使得接合线在接合线柱和半导体管芯之间延伸。包装装置还包括壳体，其包围半导体管芯，集管，接合线和接合线柱，形成绝缘的封装装置。

8. 发明申请

US20060076589A1 PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
标题翻译： PIN光电二极管结构和减少介电分层的制造工艺
公开(公告)号：US20060076589A1
公开(公告)日：2006-04-13
申请号：US11079708
申请日：2005-03-14
申请人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
发明人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
IPC分类号： H01L31/113
CPC分类号： H01L31/02161 , H01L31/105
摘要： A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
摘要翻译： PIN光电二极管，以及制造PIN光电二极管的方法，该光电二极管降低了介质分层并提高了器件可靠性。该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

9. 发明申请

US20050179107A1 Low doped layer for nitride-based semiconductor device 失效
标题翻译：用于氮化物基半导体器件的低掺杂层
公开(公告)号：US20050179107A1
公开(公告)日：2005-08-18
申请号：US10780526
申请日：2004-02-17
申请人： Milan Pophristic , Michael Murphy , Richard Stall , Bryan Shelton , Linlin Liu , Alex Ceruzzi
发明人： Milan Pophristic , Michael Murphy , Richard Stall , Bryan Shelton , Linlin Liu , Alex Ceruzzi
IPC分类号： H01L21/28 , H01L29/15 , H01L29/20 , H01L29/45 , H01L29/47 , H01L29/778 , H01L29/872 , H01L27/095
CPC分类号： H01L29/452 , H01L29/157 , H01L29/2003 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
摘要翻译：通过在另一层上形成掺杂和未掺杂的氮化物半导体材料的交替子层，通过调制掺杂形成可重复且均匀的低掺杂层。肖特基二极管由设置在更高掺杂的氮化物半导体层顶上的这种低掺杂氮化物半导体层形成。当器件正向偏置时，所得器件具有低导通电阻，器件反向偏置时具有高击穿电压。

10. 发明授权

US08319256B2 Layout design for a high power, GaN-based FET 有权
标题翻译：高功率GaN基FET的布局设计
公开(公告)号：US08319256B2
公开(公告)日：2012-11-27
申请号：US12821492
申请日：2010-06-23
申请人： Linlin Liu , Milan Pophristic , Boris Peres
发明人： Linlin Liu , Milan Pophristic , Boris Peres
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7786 , H01L29/0657 , H01L29/2003 , H01L29/41758 , H01L29/42316
摘要： A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.
摘要翻译： FET包括衬底，设置在衬底上的缓冲层，设置在缓冲层上的沟道层和设置在沟道层上的阻挡层。源极，栅极和漏极电极位于阻挡层的上方并沿其纵向方向延伸。通道和阻挡层的一部分限定沿纵向方向延伸的台面，并且源电极和漏电极延伸超过台面的边缘。栅电极沿着台面的边缘侧壁延伸。导电源互连设置在缓冲层之上并且具有电连接到源电极的第一端。第一介电层设置在缓冲层之上并且在源互连上。在第一电介质层中形成栅极通孔。导电栅极节点沿着缓冲层延伸并且电连接沿着台面的侧壁延伸的栅电极的部分。栅极焊盘设置在与台面相邻的第一电介质层上。导电栅极连接条位于栅极节点上方并与其接触。栅极条与栅极焊盘电接触。源极通孔形成在第一电介质层中，并且在源极通孔中形成源极焊盘。导电源互连具有与源极焊盘电接触的第二端。

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