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    • 2. 发明授权
    • Method of generating run length limited (RLL) code having improved DC suppression capability and modulation/demodulation method of the generated RLL code
    • 产生具有改善的DC抑制能力的行程限制(RLL)码和生成的RLL码的调制/解调方法的方法
    • US06268810B1
    • 2001-07-31
    • US09522446
    • 2000-03-09
    • Jae-seong ShimYong-kwang Won
    • Jae-seong ShimYong-kwang Won
    • H03M700
    • G11B20/1426H03M5/14H03M7/46
    • A method of generating a run length limited (RLL) code having improved direct current (DC) suppression capability and modulation and demodulation methods of the generated RLL code. According to the method of generating the RLL codes, code words that satisfy a (d, k) run length constraint are generated. By allocating main code groups, in which a code word can be duplicated depending on the characteristics of the generated codeword and code words of each main code group are allocated in consideration of a code word sum value (CSV) parameter, which represents the DC value in a code word, and an inverse characteristic of an INV parameter, which predicts the transition direction of digital sum value (DSV) of the next code word, and allocating decision groups for differentiating the duplicated code words, by using some of the code words, which are already used in main code group, as code words for DSV groups for the DC suppression, the number of code word bits can be reduced and the recording density increases, while improving the DC suppression capability.
    • 一种生成具有改进的直流(DC)抑制能力和生成的RLL码的调制和解调方法的游程长度限制(RLL)码的方法。 根据生成RLL码的方法,生成满足(d,k)游程长度约束的码字。 通过分配主代码组,其中可以根据所生成的代码字的特性和每个主代码组的代码字来复制代码字,这是考虑到代码字总和值(CSV)参数来分配的,其代表DC值 在代码字中,以及INV参数的逆特性,其预测下一个代码字的数字和值(DSV)的转换方向,并且通过使用一些代码字来分配用于区分重复的代码字的决定组 已经在主代码组中使用,作为用于DC抑制的DSV组的代码字,可以减少代码字比特的数量并且记录密度增加,同时提高DC抑制能力。
    • 4. 发明授权
    • Circuit for recovering digital clock signal and method thereof
    • 电路恢复数字时钟信号及其方法
    • US06404363B1
    • 2002-06-11
    • US09566720
    • 2000-05-09
    • Hyun-soo ParkJae-seong ShimYong-kwang Won
    • Hyun-soo ParkJae-seong ShimYong-kwang Won
    • H03M100
    • G11B20/10037G11B20/10203G11B20/1403H03L7/0807H03L7/087H03L7/113H04L7/033H04L7/0331H04L7/0334
    • A circuit for recovering a digital clock signal and a method therefor is disclosed. The digital clock recovery circuit includes an analog-to-digital (A/D) converter and asymmetry corrector for converting a received analog signal into digital data and providing corrected digital data corrected by a binarization level which traces the center value of the received signal, a frequency error detector for detecting a frequency error from the corrected digital data, a phase error detector for detecting a phase error from the corrected digital data, and a digital low pass filter (LPF) for providing the frequency error and the phase error as a control voltage. It is possible to trace the asymmetry of the received signal more sensitively than in the conventional technology by realizing an asymmetry corrector for correcting the asymmetry of the digital data which has undergone the analog-to-digital (A/D) conversion, the phase error detector, and the LPF by a digital circuit, thus generating a system clock signal and to improve the reliability of the system by stably generating the system clock signal.
    • 公开了一种用于恢复数字时钟信号的电路及其方法。 数字时钟恢复电路包括模拟数字(A / D)转换器和不对称校正器,用于将接收到的模拟信号转换成数字数据,并提供校正的数字数据,该数字数据通过追踪接收信号的中心值的二值化电平进行校正, 用于从校正的数字数据中检测频率误差的频率误差检测器,用于从校正的数字数据检测相位误差的相位误差检测器,以及用于将频率误差和相位误差提供为 控制电压。 通过实现用于校正经过模数(A / D)转换的数字数据的不对称性的不对称校正器,可以比常规技术更灵敏地追踪接收信号的不对称性,相位误差 检测器和LPF,从而产生系统时钟信号,并通过稳定地产生系统时钟信号来提高系统的可靠性。
    • 7. 发明授权
    • Code generation and allocation apparatus
    • 代码生成和分配设备
    • US07616135B2
    • 2009-11-10
    • US12027317
    • 2008-02-07
    • Jae-seong ShimKi-hyun KimHyun-soo ParkKiu-hae JungIqbal Mahboob
    • Jae-seong ShimKi-hyun KimHyun-soo ParkKiu-hae JungIqbal Mahboob
    • H03M7/00
    • G11B20/1426G11B2020/1457H03M5/145H03M7/46
    • A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.
    • 一种产生和分配码字的方法包括:当前一个码字“a”和随后的码字“b”形成码流X时,将两个可选码字b1和b2之一分配为码字“b”,其中码字b1和b2具有 相反的INV值,其是指示码字中包含的“1”的数目是奇数还是偶数的参数。 当前一个码字“a”的码流和随后的码字b1为X1时,当前一个码字“a”和随后的码字b2的码流为X2时,分配码字,使得X1的INV值 并且当前面的码字“a”或者随后的码字b1(b2)(b1或b2)应该被替换为符合在码字之间给定的预定边界条件的另一码字时,X2被维持为相反。 分配码字使得能够维持码流的DC抑制能力。
    • 8. 发明授权
    • Data modulating method and apparatus, data demodulating method and apparatus, and code arranging method
    • 数据调制方法及装置,数据解调方法及装置及代码排列方法
    • US07450034B2
    • 2008-11-11
    • US11943794
    • 2007-11-21
    • Jae-seong ShimJin-han KimKiu-hae Jung
    • Jae-seong ShimJin-han KimKiu-hae Jung
    • H03M7/00
    • G11B20/1426H03M5/145
    • In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.
    • 在数据解调方法和装置以及代码排列方法中,多路复用器将预定长度分割的输入数据流复用到多种类型的伪随机数据流中,该多个类型的伪随机数据流使用预定比特的多路复用信息, 的伪随机数据流。 编码器RLL调制多种类型的伪随机数据流以创建包括最小DC分量的调制码流。 复用器通过使用多路复用信息不断地对输入数据流进行加扰来产生随机数据流。 编码器弱无DC的RLL调制每个复用的数据流,而不使用添加了附加位的DC控制子码转换表,并且在多路复用的RLL调制码流之间提供包括最小DC分量的码流。