会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Data reproduction apparatus for optical disc system
    • 光盘系统的数据再现装置
    • US06307822B1
    • 2001-10-23
    • US09443155
    • 1999-11-18
    • Jae-Seong ShimYong-Kwang WonHyun-Soo ParkIl-Kwan Kim
    • Jae-Seong ShimYong-Kwang WonHyun-Soo ParkIl-Kwan Kim
    • G11B509
    • G11B20/10009G11B20/1426
    • A data reproduction apparatus for an optical disc system is provided. Included is an analog-to-digital converter (ADC) for sampling an input RF signal and outputting the sampled result, an adder for adding the sampled signal and an asymmetry correction signal. The added signal is output. A blank/defect detector is provided for generating a blank detection signal if no change in data is detected from the added signal during a predetermined interval of time. A correction signal generator is provided for calculating a digital sum value (DSV) from the received added signal, generating an asymmetry correction signal based on the calculated DSV, and outputting the generated asymmetry correction signal to the adder. A waveform equalizer is provided for waveform-equalizing the added signal. A decoder is provided for decoding the waveform-equalized signal and outputting the result. The correction signal corrector temporarily stops a DSV calculation operation with respect to the interval of the corresponding added signal, if the blank detection signal is output. Thus, an asymmetry of the RF signal is corrected to enhance quality of the reproduced data.
    • 提供了一种用于光盘系统的数据再现装置。 包括用于对输入RF信号进行采样并输出采样结果的模数转换器(ADC),用于将采样信号相加的加法器和不对称校正信号。 添加的信号被输出。 提供空白/缺陷检测器,用于在预定的时间间隔期间,如果在添加的信号中没有检测到数据变化,则产生空白检测信号。 提供校正信号发生器,用于根据接收到的加法信号计算数字和值(DSV),基于所计算的DSV产生不对称校正信号,并将所生成的不对称校正信号输出到加法器。 提供了波形均衡器,用于对添加的信号进行波形均衡。 提供解码器,用于对波形均衡的信号进行解码并输出结果。 如果输出空白检测信号,则校正信号校正器临时停止关于相应的相加信号的间隔的DSV计算操作。 因此,校正RF信号的不对称性以提高再现数据的质量。
    • 4. 发明授权
    • Method of detecting frequency of digital phase locked loop
    • 数字锁相环频率检测方法
    • US06580775B1
    • 2003-06-17
    • US09449735
    • 1999-11-26
    • Hyun-Soo ParkJae-Seong ShimYong-Kwang Won
    • Hyun-Soo ParkJae-Seong ShimYong-Kwang Won
    • H03D324
    • H03L7/091G01R23/10G11B20/1403H03L7/113
    • A method of detecting a frequency of a digital phase locked loop in an optical disc reproduction and/or recording apparatus, which includes (a) detecting an edge point of an input signal, (b) sampling a previous and following input signal on the basis of the detected edge point into a predetermined frequency, (c) counting a number of reference clock signals between the detected edge point and a sample which is positioned previously, adding a count value and an interval of time corresponding to the count value to obtain a frequency count value at the edge point, and (e) comparing the obtained frequency count value with a predetermined reference value, to enhance the frequency according to the comparison result can detect frequency having high resolution with only a reference clock frequency without heightening a frequency of a reference clock signal, to thereby enhance the quality of data. The frequency having the high resolution with only the reference clock frequency without heightening the frequency of the reference clock signal is detected, to thereby enhance the quality of data.
    • 一种在光盘再现和/或记录装置中检测数字锁相环的频率的方法,包括:(a)检测输入信号的边沿点,(b)基于上述和之后的输入信号进行采样 (c)计数检测到的边缘点与先前位于的样本之间的参考时钟信号的数量,增加与计数值相对应的计数值和时间间隔,以获得 在边缘点处的频率计数值,以及(e)将获得的频率计数值与预定参考值进行比较,以根据比较结果增强频率,可以仅利用参考时钟频率来检测具有高分辨率的频率,而不增加频率 一个参考时钟信号,从而提高数据的质量。 检测到仅具有参考时钟频率的高分辨率的频率而不增加参考时钟信号的频率,从而提高数据的质量。
    • 6. 发明授权
    • Circuit for recovering digital clock signal and method thereof
    • 电路恢复数字时钟信号及其方法
    • US06404363B1
    • 2002-06-11
    • US09566720
    • 2000-05-09
    • Hyun-soo ParkJae-seong ShimYong-kwang Won
    • Hyun-soo ParkJae-seong ShimYong-kwang Won
    • H03M100
    • G11B20/10037G11B20/10203G11B20/1403H03L7/0807H03L7/087H03L7/113H04L7/033H04L7/0331H04L7/0334
    • A circuit for recovering a digital clock signal and a method therefor is disclosed. The digital clock recovery circuit includes an analog-to-digital (A/D) converter and asymmetry corrector for converting a received analog signal into digital data and providing corrected digital data corrected by a binarization level which traces the center value of the received signal, a frequency error detector for detecting a frequency error from the corrected digital data, a phase error detector for detecting a phase error from the corrected digital data, and a digital low pass filter (LPF) for providing the frequency error and the phase error as a control voltage. It is possible to trace the asymmetry of the received signal more sensitively than in the conventional technology by realizing an asymmetry corrector for correcting the asymmetry of the digital data which has undergone the analog-to-digital (A/D) conversion, the phase error detector, and the LPF by a digital circuit, thus generating a system clock signal and to improve the reliability of the system by stably generating the system clock signal.
    • 公开了一种用于恢复数字时钟信号的电路及其方法。 数字时钟恢复电路包括模拟数字(A / D)转换器和不对称校正器,用于将接收到的模拟信号转换成数字数据,并提供校正的数字数据,该数字数据通过追踪接收信号的中心值的二值化电平进行校正, 用于从校正的数字数据中检测频率误差的频率误差检测器,用于从校正的数字数据检测相位误差的相位误差检测器,以及用于将频率误差和相位误差提供为 控制电压。 通过实现用于校正经过模数(A / D)转换的数字数据的不对称性的不对称校正器,可以比常规技术更灵敏地追踪接收信号的不对称性,相位误差 检测器和LPF,从而产生系统时钟信号,并通过稳定地产生系统时钟信号来提高系统的可靠性。
    • 7. 发明授权
    • Modulation code encoder and/or decoder
    • 调制码编码器和/或解码器
    • US5767798A
    • 1998-06-16
    • US684213
    • 1996-07-19
    • Yong-kwang Won
    • Yong-kwang Won
    • G11B20/10H03M5/14H03M7/00
    • H03M5/145
    • Modulation code encoder/decoder for a (2,9) RLL modulation code are provided. The modulation code encoder includes a serial-to-parallel converter, a controller, an inverter, a first and second memory and a multiplexer, and the modulation code decoder includes a serial-to-parallel converter, a controller, an inverter, a first and second memory, a first multiplexer, a delay circuit, a selection signal output portion, a second multiplexer and a parallel-to-serial converter. The modulation code encoder/decoder can be applied to a magneto-optical disk, magnetic tape and hard disk drive (HDD) in which high-density recording is required since the error correction capacity is enhanced by providing a decoder which performs an overlapped decoding operation with respect to the (2,9) RLL modulation code.
    • 提供了(2,9)RLL调制码的调制码编码器/解码器。 调制码编码器包括串并转换器,控制器,反相器,第一和第二存储器和多路复用器,并且调制码解码器包括串并转换器,控制器,逆变器,第一 第二存储器,第一多路复用器,延迟电路,选择信号输出部分,第二多路复用器和并 - 串行转换器。 调制码编码器/解码器可以应用于需要高密度记录的磁光盘,磁带和硬盘驱动器(HDD),因为通过提供执行重叠解码操作的解码器来增强纠错能力 相对于(2,9)RLL调制码。
    • 10. 发明授权
    • Method of generating run length limited (RLL) code having improved DC suppression capability and modulation/demodulation method of the generated RLL code
    • 产生具有改善的DC抑制能力的行程限制(RLL)码和生成的RLL码的调制/解调方法的方法
    • US06268810B1
    • 2001-07-31
    • US09522446
    • 2000-03-09
    • Jae-seong ShimYong-kwang Won
    • Jae-seong ShimYong-kwang Won
    • H03M700
    • G11B20/1426H03M5/14H03M7/46
    • A method of generating a run length limited (RLL) code having improved direct current (DC) suppression capability and modulation and demodulation methods of the generated RLL code. According to the method of generating the RLL codes, code words that satisfy a (d, k) run length constraint are generated. By allocating main code groups, in which a code word can be duplicated depending on the characteristics of the generated codeword and code words of each main code group are allocated in consideration of a code word sum value (CSV) parameter, which represents the DC value in a code word, and an inverse characteristic of an INV parameter, which predicts the transition direction of digital sum value (DSV) of the next code word, and allocating decision groups for differentiating the duplicated code words, by using some of the code words, which are already used in main code group, as code words for DSV groups for the DC suppression, the number of code word bits can be reduced and the recording density increases, while improving the DC suppression capability.
    • 一种生成具有改进的直流(DC)抑制能力和生成的RLL码的调制和解调方法的游程长度限制(RLL)码的方法。 根据生成RLL码的方法,生成满足(d,k)游程长度约束的码字。 通过分配主代码组,其中可以根据所生成的代码字的特性和每个主代码组的代码字来复制代码字,这是考虑到代码字总和值(CSV)参数来分配的,其代表DC值 在代码字中,以及INV参数的逆特性,其预测下一个代码字的数字和值(DSV)的转换方向,并且通过使用一些代码字来分配用于区分重复的代码字的决定组 已经在主代码组中使用,作为用于DC抑制的DSV组的代码字,可以减少代码字比特的数量并且记录密度增加,同时提高DC抑制能力。