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1. 发明授权

US06677217B2 Methods for manufacturing integrated circuit metal-insulator-metal capacitors including hemispherical grain lumps 失效
标题翻译：用于制造集成电路金属 - 绝缘体 - 金属电容器的方法包括半球形颗粒块
公开(公告)号：US06677217B2
公开(公告)日：2004-01-13
申请号：US10180277
申请日：2002-06-26
申请人： Jae-hyun Joo , Wan-don Kim , Seok-jun Won , Soon-yeon Park
发明人： Jae-hyun Joo , Wan-don Kim , Seok-jun Won , Soon-yeon Park
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L28/55 , H01L28/60 , H01L28/90
摘要： The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.
摘要翻译： MIM电容器的有效面积通过形成包括半球形颗粒的下部电极而增加。通过在氧气和/或氮气气氛中热处理金属层，从而氧化金属层的表面或生长金属层的晶粒，形成半球状晶粒块。 MIM电容器可以由Pt，Ru，Rh，Os，Ir或Pd形成，并且半球状晶粒块可以由Pt，Ru，Rh，Os，Ir或Pd形成。由于金属层在下电极的形成期间主要进行热处理，所以可以降低由于在形成介电层和上层之后的热处理而使下电极的表面形态快速变化的程度电极。

2. 发明授权

US06472319B2 Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment 失效
标题翻译：通过两步热处理制造半导体存储器件电容器的方法
公开(公告)号：US06472319B2
公开(公告)日：2002-10-29
申请号：US09851910
申请日：2001-05-09
申请人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
发明人： Seok-jun Won , Yun-jung Lee , Soon-yeon Park , Cha-young Yoo , Doo-sup Hwang , Eun-ae Chung , Wan-don Kim
IPC分类号： H01L2144
CPC分类号： H01L28/55 , H01L28/65
摘要： A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.
摘要翻译：提供了通过两步热处理制造半导体存储器件的电容器的方法。在半导体衬底上形成下电极。在下电极上形成电介质层。在电介质层上形成由贵金属形成的上电极。具有上电极的所得物在包含氧的第一气氛下进行第一热处理，所述第一气氛在第一温度下被选择在低于上电极的氧化温度的200-600℃的范围内。第一热处理产物在第二温度下在没有氧的第二气氛下进行第二热处理，第二温度选择在比第一温度高的300-900℃的范围内。

3. 发明授权

US06649502B2 Methods of forming multilayer dielectric regions using varied deposition parameters 失效
公开(公告)号：US06649502B2
公开(公告)日：2003-11-18
申请号：US09859168
申请日：2001-05-16
申请人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
发明人： Cha-young Yoo , Han-jin Lim , Wan-don Kim , Se-jin Lee , Soon-yeon Park , Yong-kuk Jeong , Han-mei Choi , Gyung-hoon Hong , Seok-jun Won
IPC分类号： H01L213205
CPC分类号： H01L21/02183 , C23C16/405 , C23C16/45557 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L28/40 , H01L28/56
摘要： A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C. and a pressure in a range from about 0.1 Torr to about 10.0 Torr during formation of a second tantalum oxide layer.

4. 发明授权

US07700454B2 Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities 有权
标题翻译：通过起皱包含高比例杂质的层来形成集成电路电极和电容器的方法
公开(公告)号：US07700454B2
公开(公告)日：2010-04-20
申请号：US11462178
申请日：2006-08-03
申请人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
发明人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L27/1085
摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
摘要翻译：提供一种制造均匀起皱的电容器下电极而不需要进行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。形成第一导电层。然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。然后可以形成电介质层和上电容器电极。

5. 发明申请

US20060263977A1 METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES 有权
标题翻译：形成集成电路电容器和电容器的方法，包括一个包含高达百分之百的包层
公开(公告)号：US20060263977A1
公开(公告)日：2006-11-23
申请号：US11462178
申请日：2006-08-03
申请人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
发明人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
IPC分类号： H01L21/8242
CPC分类号： H01L28/84 , H01L27/1085
摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
摘要翻译：提供一种制造均匀起皱的电容器下电极而不需要执行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。形成第一导电层。然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。然后可以形成电介质层和上电容器电极。

6. 发明授权

US06613629B2 Methods for manufacturing storage nodes of stacked capacitors 有权
公开(公告)号：US06613629B2
公开(公告)日：2003-09-02
申请号：US10213856
申请日：2002-08-07
申请人： Wan-don Kim , Cha-young Yoo , Jae-hyun Joo , Seok-jun Won
发明人： Wan-don Kim , Cha-young Yoo , Jae-hyun Joo , Seok-jun Won
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L27/10852 , H01L28/55
摘要： Methods for manufacturing a node of a stacked capacitor are provided. A first dielectric layer having a contact plug therein is formed on an integrated circuit substrate. A second dielectric layer including a storage node hole adjacent the contact plug is formed on the first dielectric layer. A conductive layer is deposited into the storage node hole and on the second dielectric layer. The conductive layer on the second dielectric layer is removed to provide a conductive storage node in the storage node hole. After the conductive layer on the second dielectric layer is removed, the conductive storage node is heat treated to reflow the conductive storage node before additional layers are formed on the conductive storage node.

7. 发明申请

US20050161727A1 Integrated circuit devices having a metal-insulator-metal (MIM) capacitor 审中-公开
标题翻译：具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件
公开(公告)号：US20050161727A1
公开(公告)日：2005-07-28
申请号：US11083874
申请日：2005-03-18
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

8. 发明授权

US06884673B2 Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor 有权
标题翻译：形成具有金属 - 绝缘体 - 金属（MIM）电容器的集成电路器件的方法
公开(公告)号：US06884673B2
公开(公告)日：2005-04-26
申请号：US10160646
申请日：2002-05-31
申请人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
发明人： Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L28/60 , H01L27/10855 , H01L28/91
摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
摘要翻译：在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。电介质层位于下电极上，电容器的上电极位于电介质层上。在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。接触塞设置在阻挡层上的孔中。电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。电介质层位于下电极上，电容器的上电极位于电介质层上。

9. 发明授权

US06815221B2 Method for manufacturing capacitor of semiconductor memory device controlling thermal budget 有权
标题翻译：制造控制热预算的半导体存储器件电容器的方法
公开(公告)号：US06815221B2
公开(公告)日：2004-11-09
申请号：US10105181
申请日：2002-03-25
申请人： Wan-don Kim , Cha-young Yoo , Doo-sup Hwang , Jae-hyun Joo , Eun-ae Chung , Yong-kuk Jeong
发明人： Wan-don Kim , Cha-young Yoo , Doo-sup Hwang , Jae-hyun Joo , Eun-ae Chung , Yong-kuk Jeong
IPC分类号： H01G706
CPC分类号： H01L28/55 , H01L28/60 , H01L28/91
摘要： A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.
摘要翻译：提供了一种通过控制热预算来制造半导体存储器件的电容器的方法。在制造半导体存储器件的电容器的方法中，在半导体衬底上形成下电极。下电极用第一热预算进行热处理。在热处理的下电极上形成电介质层。通过用小于第一热预算的第二热预算对介电层进行热处理来使介质层结晶。

10. 发明授权

US06806139B2 Method of fabricating a MIM capacitor using etchback 有权
标题翻译：使用回蚀法制造MIM电容器的方法
公开(公告)号：US06806139B2
公开(公告)日：2004-10-19
申请号：US10266606
申请日：2002-10-09
申请人： Wan-don Kim , Jae-hyun Joo , Cha-young Yoo
发明人： Wan-don Kim , Jae-hyun Joo , Cha-young Yoo
IPC分类号： H01L2100
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/55 , H01L28/65
摘要： A method of fabricating a metal-insulator-metal (MIM) capacitor of a semiconductor device having an upper and lower electrode formed of metal is provided. Portions of a conductive layer for a lower electrode on inner walls of holes are not removed. Portions of the conductive layer for a lower electrode outside the holes are selectively etched back and node-separated.
摘要翻译：提供了一种制造具有由金属形成的上电极和下电极的半导体器件的金属 - 绝缘体 - 金属（MIM）电容器的方法。用于孔的内壁上的下电极的导电层的部分不被去除。用于孔外的下电极的导电层的部分被选择性地回蚀和分离。

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