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1. 发明申请

US20070029597A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：高压半导体器件
公开(公告)号：US20070029597A1
公开(公告)日：2007-02-08
申请号：US11460755
申请日：2006-07-28
申请人： Jae-gil Lee , Kyu-hyun Lee , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Kyu-hyun Lee , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7802
摘要： Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and P pillars of P conductivity type, arranged alternately in a direction from a center portion of the active region to an outer portion thereof to encircle each other in a horizontal direction. The N and P pillars are formed in a closed shape.
摘要翻译：提供一种高电压半导体器件，其被构造成使得P和N电荷的量在整个漂移区域中平衡，从而防止器件击穿特性的劣化。高电压半导体器件包括N个导电型的N支柱和P导电型的P支柱的有源区域，其在从有源区域的中心部分到其外部部分的方向上交替布置以在水平方向上彼此包围方向。 N和P柱形成为封闭形状。

2. 发明授权

US07645659B2 Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same 有权
标题翻译：使用硅衬底作为场效应层的功率半导体器件及其制造方法
公开(公告)号：US07645659B2
公开(公告)日：2010-01-12
申请号：US11289823
申请日：2005-11-30
申请人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
发明人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
IPC分类号： H01L23/58
CPC分类号： H01L29/7395 , H01L29/66333 , H01L2924/0002 , H01L2924/00
摘要： Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.
摘要翻译：提供了使用硅衬底作为FS层的功率半导体器件及其制造方法。制备第一导电类型的半导体衬底。在半导体衬底的一个表面上生长外延层。这里，以比半导体衬底低的浓度掺杂外延层，并且旨在用作漂移区域。在外延层的预定区域中形成第二导电类型的基极区域。第一导电类型的发射极区域形成在基极区域的预定区域中。在外延层的发射极区域和漂移区域之间的基极区域上形成具有栅极绝缘层的栅电极。研磨半导体衬底的后表面以减小半导体衬底的厚度，由此设置第一导电类型的FS区。在FS区域的半导体衬底的地表面上形成第二导电类型的集电极区域，从而形成FS-IGBT。

3. 发明申请

US20070120215A1 Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same 有权
标题翻译：使用硅衬底作为场效应层的功率半导体器件及其制造方法
公开(公告)号：US20070120215A1
公开(公告)日：2007-05-31
申请号：US11289823
申请日：2005-11-30
申请人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
发明人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
IPC分类号： H01L23/58
CPC分类号： H01L29/7395 , H01L29/66333 , H01L2924/0002 , H01L2924/00
摘要： Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.
摘要翻译：提供了使用硅衬底作为FS层的功率半导体器件及其制造方法。制备第一导电类型的半导体衬底。在半导体衬底的一个表面上生长外延层。这里，以比半导体衬底低的浓度掺杂外延层，并且旨在用作漂移区域。在外延层的预定区域中形成第二导电类型的基极区域。第一导电类型的发射极区域形成在基极区域的预定区域中。在外延层的发射极区域和漂移区域之间的基极区域上形成具有栅极绝缘层的栅电极。研磨半导体衬底的后表面以减小半导体衬底的厚度，由此设置第一导电类型的FS区。在FS区域的半导体衬底的地表面上形成第二导电类型的集电极区域，从而形成FS-IGBT。

4. 发明授权

US06518624B2 Trench-gate power semiconductor device preventing latch-up and method for fabricating the same 失效
公开(公告)号：US06518624B2
公开(公告)日：2003-02-11
申请号：US09734016
申请日：2000-12-12
申请人： Hyun-chul Kim , Chong-man Yun , Kyu-hyun Lee , Ju-il Kim
发明人： Hyun-chul Kim , Chong-man Yun , Kyu-hyun Lee , Ju-il Kim
IPC分类号： H01L2976
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/66348 , H01L29/7397
摘要： A trench-gate power semiconductor device and a method for fabricating the same are provided. The trench-gate power semiconductor device includes a semiconductor substrate of a first conductivity type used as a collector region, a buffer layer of a second conductivity type formed on the semiconductor substrate, a drift region of a second conductivity type formed on the buffer layer, a base region of a first conductivity type formed on the drift region, a gate dielectric layer formed on the surface of a trench which is formed down to a predetermined depth into the drift region and surrounds the base region, a gate electrode formed on the gate dielectric layer, an emitter region of a second conductivity type contacting both the surface of the base region and an upper sidewall of the trench in the base region, the emitter region contains a first emitter region formed so as to be extended to a predetermined length along the sidewall of the trench and to be alternately arranged in the base region and a second emitter region extended to a predetermined length from the first emitter to the center of the base region, an emitter electrode formed so as to be electrically connected to the first emitter region through a part of the second emitter region, and a collector electrode formed so as to be electrically connected to the semiconductor substrate.

5. 发明授权

US06890841B2 Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby 有权
标题翻译：形成集成电路存储器件的方法包括以交错图案布置的多个着陆焊盘孔和由此形成的集成电路存储器件
公开(公告)号：US06890841B2
公开(公告)日：2005-05-10
申请号：US10442481
申请日：2003-05-21
申请人： Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
发明人： Kyu-hyun Lee , Tae-young Chung , Chang-hyun Cho , Yang-keun Park , Sang-bum Kim
IPC分类号： H01L21/28 , H01L21/02 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L21/20 , H01L29/94
CPC分类号： H01L28/60 , H01L21/76895 , H01L28/91 , Y10S257/908
摘要： An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.
摘要翻译：通过在衬底上形成层间绝缘层来形成集成电路存储器件。在层间绝缘层中形成多个存储节点接触孔，并以图案排列。多个接触插塞分别形成在多个存储节点接触孔中。在层间绝缘层上形成材料层，其具有分别露出多个接触插塞的多个着陆焊盘孔，多个着陆焊盘孔以相对于存储器的图案偏移的图案布置节点接触孔。多个着陆焊盘形成在多个着陆焊盘孔中，分别连接到多个接触插塞。形成分别连接到多个着陆焊盘的多个存储节点。

6. 发明授权

US06262470B1 Trench-type insulated gate bipolar transistor and method for making the same 有权
标题翻译：沟槽型绝缘栅双极晶体管
公开(公告)号：US06262470B1
公开(公告)日：2001-07-17
申请号：US09369487
申请日：1999-08-05
申请人： Kyu-hyun Lee , Tae-hoon Kim
发明人： Kyu-hyun Lee , Tae-hoon Kim
IPC分类号： H01L27082
CPC分类号： H01L29/66348 , H01L29/7397
摘要： A trench-type insulated gate bipolar transistor in which a channel stop region is partially formed between an n-type high-concentration emitter region and a p-type base region in which a conductive channel is to be formed. The channel stop region is doped with p-type impurities at high concentration. A portion of the emitter region directly contact the base region, and the other portion has the channel stop region disposed between itself and the base region without directly contacting the base region. At the portion where the channel stop region is interposed, an electron current from the emitter region does not flow vertically into a drift region, but horizontally moves to a direct contacts portion between the emitter region and the base region and then vertically flows to the drift region via the conductive channel. The horizontally-flowing electron current within the emitter region causes a voltage drop, thus reducing the voltage difference at the junction between the emitter region and the base region. Therefore, a latch-up phenomenon, in which a parasitic thyristor is turned on, is suppressed.
摘要翻译：沟槽型绝缘栅双极晶体管，其中沟道阻挡区域部分地形成在要形成导电沟道的n型高浓度发射极区域和p型基极区域之间。通道停止区以高浓度掺杂p型杂质。发射极区域的一部分直接接触基极区域，另一部分具有设置在其与基极区域之间的沟道阻挡区域，而不直接接触基极区域。在插入通道停止区域的部分，来自发射极区域的电子电流不会垂直流入漂移区域，而是水平移动到发射极区域和基极区域之间的直接接触部分，然后垂直地流到漂移区域区域。发射极区域内的水平流动的电子电流引起电压降，从而降低发射极区域和基极区域之间的结处的电压差。因此，抑制了寄生晶闸管导通的闭锁现象。

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