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1. 发明授权

US06518624B2 Trench-gate power semiconductor device preventing latch-up and method for fabricating the same 失效
公开(公告)号：US06518624B2
公开(公告)日：2003-02-11
申请号：US09734016
申请日：2000-12-12
申请人： Hyun-chul Kim , Chong-man Yun , Kyu-hyun Lee , Ju-il Kim
发明人： Hyun-chul Kim , Chong-man Yun , Kyu-hyun Lee , Ju-il Kim
IPC分类号： H01L2976
CPC分类号： H01L29/0696 , H01L29/1095 , H01L29/66348 , H01L29/7397
摘要： A trench-gate power semiconductor device and a method for fabricating the same are provided. The trench-gate power semiconductor device includes a semiconductor substrate of a first conductivity type used as a collector region, a buffer layer of a second conductivity type formed on the semiconductor substrate, a drift region of a second conductivity type formed on the buffer layer, a base region of a first conductivity type formed on the drift region, a gate dielectric layer formed on the surface of a trench which is formed down to a predetermined depth into the drift region and surrounds the base region, a gate electrode formed on the gate dielectric layer, an emitter region of a second conductivity type contacting both the surface of the base region and an upper sidewall of the trench in the base region, the emitter region contains a first emitter region formed so as to be extended to a predetermined length along the sidewall of the trench and to be alternately arranged in the base region and a second emitter region extended to a predetermined length from the first emitter to the center of the base region, an emitter electrode formed so as to be electrically connected to the first emitter region through a part of the second emitter region, and a collector electrode formed so as to be electrically connected to the semiconductor substrate.

2. 发明申请

US20070029597A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：高压半导体器件
公开(公告)号：US20070029597A1
公开(公告)日：2007-02-08
申请号：US11460755
申请日：2006-07-28
申请人： Jae-gil Lee , Kyu-hyun Lee , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Kyu-hyun Lee , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/7802
摘要： Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and P pillars of P conductivity type, arranged alternately in a direction from a center portion of the active region to an outer portion thereof to encircle each other in a horizontal direction. The N and P pillars are formed in a closed shape.
摘要翻译：提供一种高电压半导体器件，其被构造成使得P和N电荷的量在整个漂移区域中平衡，从而防止器件击穿特性的劣化。高电压半导体器件包括N个导电型的N支柱和P导电型的P支柱的有源区域，其在从有源区域的中心部分到其外部部分的方向上交替布置以在水平方向上彼此包围方向。 N和P柱形成为封闭形状。

3. 发明授权

US07645659B2 Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same 有权
标题翻译：使用硅衬底作为场效应层的功率半导体器件及其制造方法
公开(公告)号：US07645659B2
公开(公告)日：2010-01-12
申请号：US11289823
申请日：2005-11-30
申请人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
发明人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
IPC分类号： H01L23/58
CPC分类号： H01L29/7395 , H01L29/66333 , H01L2924/0002 , H01L2924/00
摘要： Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.
摘要翻译：提供了使用硅衬底作为FS层的功率半导体器件及其制造方法。制备第一导电类型的半导体衬底。在半导体衬底的一个表面上生长外延层。这里，以比半导体衬底低的浓度掺杂外延层，并且旨在用作漂移区域。在外延层的预定区域中形成第二导电类型的基极区域。第一导电类型的发射极区域形成在基极区域的预定区域中。在外延层的发射极区域和漂移区域之间的基极区域上形成具有栅极绝缘层的栅电极。研磨半导体衬底的后表面以减小半导体衬底的厚度，由此设置第一导电类型的FS区。在FS区域的半导体衬底的地表面上形成第二导电类型的集电极区域，从而形成FS-IGBT。

4. 发明申请

US20070120215A1 Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same 有权
标题翻译：使用硅衬底作为场效应层的功率半导体器件及其制造方法
公开(公告)号：US20070120215A1
公开(公告)日：2007-05-31
申请号：US11289823
申请日：2005-11-30
申请人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
发明人： Chong-man Yun , Kwang-hoon Oh , Kyu-hyun Lee , Young-chull Kim
IPC分类号： H01L23/58
CPC分类号： H01L29/7395 , H01L29/66333 , H01L2924/0002 , H01L2924/00
摘要： Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.
摘要翻译：提供了使用硅衬底作为FS层的功率半导体器件及其制造方法。制备第一导电类型的半导体衬底。在半导体衬底的一个表面上生长外延层。这里，以比半导体衬底低的浓度掺杂外延层，并且旨在用作漂移区域。在外延层的预定区域中形成第二导电类型的基极区域。第一导电类型的发射极区域形成在基极区域的预定区域中。在外延层的发射极区域和漂移区域之间的基极区域上形成具有栅极绝缘层的栅电极。研磨半导体衬底的后表面以减小半导体衬底的厚度，由此设置第一导电类型的FS区。在FS区域的半导体衬底的地表面上形成第二导电类型的集电极区域，从而形成FS-IGBT。

5. 发明申请

US20120161274A1 SUPERJUNCTION SEMICONDUCTOR DEVICE 审中-公开
标题翻译：超级半导体器件
公开(公告)号：US20120161274A1
公开(公告)日：2012-06-28
申请号：US13325690
申请日：2011-12-14
申请人： Jae-gil Lee , Jin-young Jung , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Jin-young Jung , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L29/06
CPC分类号： H01L29/0634
摘要： A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners. The edge p pillar has an outer region surrounding the active region and an inner region on in the sides of the active region. The active region has active p pillars and active n pillars having vertical stripe shapes. The active p pillars and the active n pillars are alternately arranged horizontally in the active region. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar.
摘要翻译：超结半导体器件包括边缘p柱，有源区和端接区。边缘p柱具有圆角的矩形环形。边缘p柱具有围绕有源区域的外部区域和有源区域的侧面中的内部区域。活性区域具有活性p柱和活性n柱，具有垂直条纹形状。有源P柱和主动n柱在水平地交替地布置在有源区中。终端区域包括交替布置在边缘p柱周围的终止n柱和端接p柱。

6. 发明授权

US08084815B2 Superjunction semiconductor device 有权
标题翻译：超结半导体器件
公开(公告)号：US08084815B2
公开(公告)日：2011-12-27
申请号：US11172455
申请日：2005-06-29
申请人： Jae-gil Lee , Jin-young Jung , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Jin-young Jung , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L29/66
CPC分类号： H01L29/0634
摘要： A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.
摘要翻译：超结半导体器件包括边缘p柱，有源区和端接区。边缘p柱具有围绕活动区域的圆角的矩形环形。有源区域包括有源n区域和具有在有源区域中以规则间隔设置的垂直条纹形状的有源p柱。活动p柱的顶端和底端与边缘p柱分离。终端区域包括交替布置在边缘p柱周围的终止n柱和端接p柱。淘汰不用于平衡p费用数量和边际p柱上部和下部的p费用中的n费用的剩余费用，或者补充n个费用以平衡p费用的数量 n的数量。

7. 发明授权

US06344676B1 Power semiconductor device having low on-resistance and high breakdown voltage 有权
标题翻译：具有低导通电阻和高击穿电压的功率半导体器件
公开(公告)号：US06344676B1
公开(公告)日：2002-02-05
申请号：US09533824
申请日：2000-03-24
申请人： Chong-man Yun , Tae-hoon Kim , Ho-cheol Jang , Young-chull Choi
发明人： Chong-man Yun , Tae-hoon Kim , Ho-cheol Jang , Young-chull Choi
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/1095 , H01L29/7395
摘要： A power semiconductor device having low on-resistance and a high breakdown voltage is disclosed. The power semiconductor device can be a high power MOS transistor or an insulation gate bipolar transistor. The power semiconductor device has unit cells formed in parallel body region strips. A highly-doped drift layer of the same conductivity type as that of a drift region is provided between adjacent body region strips in a unit cell. Both ends of each of the body region strips of the unit cell are connected to a single frame region. This prevents a depletion region of a spherical or cylindrical type from being formed on an edge of the body region, and in so doing, increases a breakdown voltage of the device.
摘要翻译：公开了具有低导通电阻和高击穿电压的功率半导体器件。功率半导体器件可以是高功率MOS晶体管或绝缘栅双极晶体管。功率半导体器件具有以平行体区带形成的单元电池。在单元电池中的相邻体区带之间设置与漂移区相同导电类型的高掺杂漂移层。单元电池的每个体区带的两端连接到单个框架区域。这防止了在体区域的边缘上形成球形或圆柱形的耗尽区，并且这样做增加了器件的击穿电压。

8. 发明申请

US20110097864A1 Method of Fabricating High-Voltage Semiconductor Device 有权
标题翻译：制造高压半导体器件的方法
公开(公告)号：US20110097864A1
公开(公告)日：2011-04-28
申请号：US12985093
申请日：2011-01-05
申请人： Jae-gil Lee , Chang-wook Kim , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Chang-wook Kim , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.
摘要翻译：一种制造高电压半导体器件的方法包括以下步骤：提供半导体层; 在所述半导体层中形成多个沟槽以在相邻沟槽之间的所述半导体层中限定出第一导电类型的多个柱，其中所述沟槽从所述半导体层的顶表面朝向所述半导体层的底表面延伸; 在每个沟槽的至少侧壁上形成第二导电类型的电荷补偿层至预定厚度，从而在每个沟槽中形成凹槽; 并且用第一导电类型的电荷补偿塞基本上填充每个凹槽。

9. 发明申请

US20080111207A1 High-Voltage Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：高压半导体器件及其制造方法
公开(公告)号：US20080111207A1
公开(公告)日：2008-05-15
申请号：US11939264
申请日：2007-11-13
申请人： Jae-gil Lee , Chang-wook Kim , Ho-cheol Jang , Chong-man Yun
发明人： Jae-gil Lee , Chang-wook Kim , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L23/00 , H01L21/44
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.
摘要翻译：高压半导体器件包括具有多个由多个沟槽限定的第一导电类型的柱的半导体层，该多个沟槽从半导体层的顶表面向其底表面延伸。第二导电类型的电荷补偿层设置在每个沟槽的至少侧壁上至预定厚度，以在每个沟槽中形成凹槽。第一导电类型的电荷补偿插头基本上填充每个沟槽。

10. 发明授权

US07276405B2 Power semiconductor device having high breakdown voltage, low on-resistance and small switching loss and method of forming the same 有权
标题翻译：具有高击穿电压，低导通电阻和小开关损耗的功率半导体器件及其形成方法
公开(公告)号：US07276405B2
公开(公告)日：2007-10-02
申请号：US11182578
申请日：2005-07-14
申请人： Young-chul Choi , Tae-hoon Kim , Ho-cheol Jang , Chong-man Yun
发明人： Young-chul Choi , Tae-hoon Kim , Ho-cheol Jang , Chong-man Yun
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7395
摘要： In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.
摘要翻译：根据本发明的一个实施例，功率半导体器件包括在半导体衬底上延伸的第一导电类型的第一漂移区。第一漂移区域具有比半导体衬底更低的杂质浓度。第一导电类型的第二漂移区域在第一漂移区域上延伸，并且具有比第一漂移区域更高的杂质浓度。第二导电类型的多个条形体区域形成在第二漂移区域的上部。第一导电类型的第三区域形成在每个体区的上部，以便在第三区域和第二漂移区域之间的每个体区域中形成沟道区域。栅电极横向延伸，但与以下绝缘：（i）每个体区中的沟道区，（ii）相邻的体区之间的第二漂移区的表面积，和（iii）每个源的表面部分地区。

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