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1. 发明授权

US6107193A Completely removal of TiN residue on dual damascence process 失效
标题翻译：完全去除TiN残留物在双重腐蚀过程中
公开(公告)号：US6107193A
公开(公告)日：2000-08-22
申请号：US22840
申请日：1998-02-12
申请人： G. S. Shiao , Min-Liang Chen , Wei-Jing Wen
发明人： G. S. Shiao , Min-Liang Chen , Wei-Jing Wen
IPC分类号： H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/32136 , H01L21/7684
摘要： A process for completely removing TiN residue existing outside contact windows is described: electrical elements are formed on a silicon substrate, an insulating layer is then formed over the entire silicon substrate, next, the insulating layer is partially etched to form metal contact windows, a TiN barrier layer and a tungsten metal layer are then sequentially deposited overlaying the insulating layer and filling into the metal contact windows, two stage CMP process is performed to remove the metal and TiN barrier layers exposed outside the contact windows respectively, finally, an dry etching step employing HCl/Cl.sub.2 plasmas is performed to make sure there is not any TiN residues left outside contact windows.
摘要翻译：描述了一种用于完全去除存在于接触窗外部的TiN残留物的方法：在硅衬底上形成电气元件，然后在整个硅衬底上形成绝缘层，接下来，绝缘层被部分蚀刻以形成金属接触窗口 TiN阻挡层和钨金属层然后顺序地沉积覆盖在绝缘层上并填充到金属接触窗中，执行两阶段CMP工艺以分别暴露在接触窗外部的金属和TiN阻挡层，最后是干蚀刻进行采用HCl / Cl 2等离子体的步骤，以确保留下接触窗口外没有任何TiN残留物。

2. 发明授权

US5946568A Self aligned method of fabricating a DRAM with improved capacitance 失效
标题翻译：制造具有改善电容的DRAM的自对准方法
公开(公告)号：US5946568A
公开(公告)日：1999-08-31
申请号：US649466
申请日：1996-05-17
申请人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
发明人： Chia-Shun Hsiao , Wei-Jing Wen , Wen-Jeng Lin , Chung-Chih Wang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/76897 , H01L28/82
摘要： A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved. The planar area of 2P can be increased by this method and not be limited by the overlap of 2C/3P.
摘要翻译：具有场板/ BL隔离工艺的自对准的DRAM芯片的固态存储器制造方法包括使用氧化物 - 多氧化物蚀刻，随后氧化或侧壁沉积（LPTEOS）来隔离场板和BL。该工艺在制造工艺中使用第一蚀刻剂和第二蚀刻剂来蚀刻BL / N +接触。在BL / N +接触蚀刻（2C蚀刻）期间，低选择性蚀刻剂首先蚀刻Ploy-3。该第一蚀刻剂应用大约一百八十秒。然后使用高Si选择性蚀刻剂进行第二蚀刻工艺，其蚀刻残余氧化物的方式。第二种蚀刻剂应用大约九十秒。侧壁上的暴露的聚合物通过氧化或沉积（LPTEOS）与接触孔隔离。在氧化过程中形成在衬底上的氧化物被各向异性腐蚀蚀刻掉。因此实现了BL / 3P的自对准。可以通过这种方法增加2P的平面面积，而不受2C / 3P的重叠的限制。

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