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1. 发明授权

US06440788B2 Implant sequence for multi-function semiconductor structure and method 失效
标题翻译：多功能半导体结构和方法的种植体序列
公开(公告)号：US06440788B2
公开(公告)日：2002-08-27
申请号：US09895159
申请日：2001-07-02
申请人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2710
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译：提供了多功能半导体器件。该器件包括并联形成的双极晶体管和FET。半导体衬底设置在绝缘层上。源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。集电极区域和源极/发射极区域之间的最短距离定义基极宽度。

2. 发明授权

US06369671B1 Voltage controlled transmission line with real-time adaptive control 有权
标题翻译：电压控制传输线具有实时自适应控制
公开(公告)号：US06369671B1
公开(公告)日：2002-04-09
申请号：US09281412
申请日：1999-03-30
申请人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01P1185
CPC分类号： G11C7/12
摘要： A semiconductor structure having a substrate, an insulator above a portion of the substrate, a conductor above the insulator; and at least two contact regions in the substrate on opposite sides of the portion of the substrate, wherein a voltage between the contact regions modulates a capacitance of the conductor.
摘要翻译：一种具有衬底的半导体结构，在衬底的一部分上方的绝缘体，绝缘体上方的导体; 以及在所述衬底的所述部分的相对侧上的所述衬底中的至少两个接触区域，其中所述接触区域之间的电压调制所述导体的电容。

3. 发明授权

US06255694B1 Multi-function semiconductor structure and method 失效
标题翻译：多功能半导体结构及方法
公开(公告)号：US06255694B1
公开(公告)日：2001-07-03
申请号：US09484198
申请日：2000-01-18
申请人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2701
CPC分类号： H01L29/7302 , H01L21/84 , H01L27/1203
摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.
摘要翻译：提供了多功能半导体器件。该器件包括并联形成的双极晶体管和FET。半导体衬底设置在绝缘层上。源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。集电极区域和源极/发射极区域之间的最短距离定义基极宽度。

4. 发明授权

US06255899B1 Method and apparatus for increasing interchip communications rates 失效
标题翻译：提高芯片间通信速率的方法和装置
公开(公告)号：US06255899B1
公开(公告)日：2001-07-03
申请号：US09388164
申请日：1999-09-01
申请人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
发明人： Claude L. Bertin , Anthony R. Bonaccio , Erik L. Hedberg , Howard L. Kalter , Thomas M. Maffitt , Jack A. Mandelman , Edward J. Nowak , William R. Tonti
IPC分类号： H01L2500
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/0652 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： An assembly is provided that includes an interposer having first and second substantially flat, opposed surfaces, and at least one speed critical signal line extending directly through the interposer from the first surface to the second surface. A first IC is coupled to the first surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. A second IC is coupled to the second surface of the interposer and has a first external connection mechanism coupled to the at least one speed critical signal line. Preferably at least one non-speed critical signal line is provided within the interposer and is coupled to a second external connection mechanism of the first IC and/or the second IC for delivering non-speed critical signals thereto or for receiving such signals therefrom. A chip carrier having a cavity formed therein also may be provided wherein the second surface of the interposer is coupled to the chip carrier and the second IC is disposed within the cavity. One or more carrier signal lines may be provided within the chip carrier and coupled between the interposer and the second IC. The first and/or the second IC also may comprise control logic adapted to select a number of drivers within either IC that drive a particular signal line.
摘要翻译：提供了一种组件，其包括具有第一和第二基本上平坦的相对表面的插入件以及至少一个直线从第一表面延伸到第二表面的速度临界信号线。第一IC耦合到插入器的第一表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。第二IC耦合到插入器的第二表面，并且具有耦合到至少一个速度临界信号线的第一外部连接机构。优选地，在插入器内提供至少一个非速度临界信号线，并且耦合到第一IC和/或第二IC的第二外部连接机构，用于向其递送非速度关键信号或用于从其接收这样的信号。还可以提供其中形成有空腔的芯片载体，其中插入器的第二表面耦合到芯片载体，并且第二IC设置在空腔内。可以在芯片载体内提供一个或多个载波信号线，并且耦合在插入器和第二IC之间。第一和/或第二IC还可以包括适于选择驱动特定信号线的IC内的多个驱动器的控制逻辑。

5. 发明授权

US5587604A Contacted body silicon-on-insulator field effect transistor 失效
标题翻译：接触体上绝缘体上的场效应晶体管
公开(公告)号：US5587604A
公开(公告)日：1996-12-24
申请号：US310691
申请日：1994-09-22
申请人： Brian J. Machesney , Jack A. Mandelman , Edward J. Nowak
发明人： Brian J. Machesney , Jack A. Mandelman , Edward J. Nowak
IPC分类号： H01L29/786 , H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L2924/0002 , Y10S148/15 , Y10S438/98
摘要： Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
摘要翻译：提出了用于形成用于SOI FET的体衬底连接器的结构和方法。该连接器在不干扰源极和漏极的装置的一侧基本上与栅极导体共同对准。因此，本体保持靠近基底电位，并且连接器为多数载体快速离开身体提供了路径。通过以不扰乱由栅极成像的电荷的方式接触SOI MOSFET器件的主体，消除寄生双极效应，同时保持SOI MOSFET器件的期望属性，例如低衬底偏置灵敏度和陡峭的次阈值斜率。通过形成与栅极导体基本上共同对准的连接器，连接使用很少或没有表面积。

6. 发明申请

US20090134463A1 SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
标题翻译：用于制造集成电路芯片的半导体结构和系统
公开(公告)号：US20090134463A1
公开(公告)日：2009-05-28
申请号：US12348344
申请日：2009-01-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, JR. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L29/78
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.
摘要翻译：一种半导体结构和用于制造集成电路芯片的系统。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。

7. 发明授权

US07163851B2 Concurrent Fin-FET and thick-body device fabrication 有权
标题翻译：并联Fin-FET和厚体器件制造
公开(公告)号：US07163851B2
公开(公告)日：2007-01-16
申请号：US10227995
申请日：2002-08-26
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L21/84
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： The present invention provides methods for fabrication of fin-type field effect transistors (FinFETs) and thick-body devices on the same chip using common masks and steps to achieve greater efficiency than prior methods. The reduction in the number of masks and steps is achieved by using common masks and steps with several scaling strategies. In one embodiment, the structure normally associated with a FinFET is created on the side of a thick silicon mesa, the bulk of which is doped to connect with a body contact on the opposite side of the mesa. The invention also includes FinFETs, thick-body devices, and chips fabricated by the methods.
摘要翻译：本发明提供了使用公共掩模和步骤在相同芯片上制造鳍式场效应晶体管（FinFET）和厚体器件的方法，以实现比现有方法更高的效率。通过使用具有多种缩放策略的常用掩模和步骤来实现掩模和步骤数量的减少。在一个实施例中，通常与FinFET相关联的结构产生在厚硅台面的一侧，该厚硅台面的大部分被掺杂以与台面的相对侧上的身体接触连接。本发明还包括FinFET，厚体器件和通过这些方法制造的芯片。

8. 发明授权

US07473970B2 Concurrent fin-fet and thick body device fabrication 有权
标题翻译：并发鳍和厚体器件制造
公开(公告)号：US07473970B2
公开(公告)日：2009-01-06
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , David M. Fried , Robert J. Gauthier, Jr. , Edward J. Nowak , Jed H. Rankin , William R. Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.
摘要翻译：集成电路芯片和半导体结构。集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。

9. 发明申请

US20080153278A1 Doped Single Crystal Silicon Silicided eFuse 有权
标题翻译：掺杂单晶硅硅胶eFuse
公开(公告)号：US20080153278A1
公开(公告)日：2008-06-26
申请号：US12043226
申请日：2008-03-06
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

10. 发明授权

US07382036B2 Doped single crystal silicon silicided eFuse 有权
标题翻译：掺杂单晶硅硅片eFuse
公开(公告)号：US07382036B2
公开(公告)日：2008-06-03
申请号：US11161320
申请日：2005-07-29
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L27/148
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

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