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    • 5. 发明专利
    • RESERVE INFORMATION CONTROL SYSTEM
    • JPS5674772A
    • 1981-06-20
    • JP15066379
    • 1979-11-22
    • JAPAN NATIONAL RAILWAYHITACHI LTD
    • MIYATA KENZOUSHIMIZU IWAOOOMORI KATSUHIROMAEHARA TOMOHARUKOSEKI TAKEYOSHIOOTANI AKIO
    • G06Q10/10G06Q10/00G06Q10/06G06Q30/06G06Q50/00
    • PURPOSE:To facilitate operation by eliminating the manual input of a control number by making it easy for a central device to discriminate between reserving and resending by adding the control number of transmitted information to be sent to the central device when an indication button for the deduction or regeneration of reserve information. CONSTITUTION:Central device 1 that adds control information updated for every reserve information is provided with update memory 3 stored with the control information to be transmitted, receiving circuit 6 that receives request information from terminal devices 8, 15 and 16, and control number comparison part 4 that compares the request information with control information in memory 3. Each of terminal devices 8, 15 and 16 is provided with transmission part 13 that generates an operation kind signal for reservation, control number memory part 11 that stores control information sent from central device 1 when the output operation is performed normally, etc. When respective indication buttons for reservation 17, deduction 18 and regeneration 19 of each of terminal device 8, 15 and 16 are operated, the control number including the control information in memory part 11 is sent to central device 1 and compared by comparison part 4 to update the contents of memory 3, so that the operation will be facilitated without inputting the control number manually.
    • 6. 发明专利
    • SEAT RESERVATION UNIT
    • JPS55112677A
    • 1980-08-30
    • JP1977179
    • 1979-02-23
    • JAPAN NATIONAL RAILWAYHITACHI LTD
    • TSUBOI KATSUEOOMORI KATSUHIROKITAJIMA HIROYUKIKIKUTA SHIGEOSATOU KIYOUSUKEMAEHARA TOMOHARU
    • G06Q30/06G06Q50/00
    • PURPOSE:To reduce the load of central unit and communication line, by constituting the seat reservation unit for railway and aircraft with the central unit and terminal unit and minimizing the ineffective call from the terminal unit to the central unit. CONSTITUTION:To the central processor 34, the reservation file 36 storing the state of seat reservation as to all the flights handled as the objective of reservation and the state of reservation display file 38 are connected and the transmission and reception unit 32 is connected to constitute the central unit. The transmission and reception unit 12 for a plurality of terminal units is connected to the unit 32 of the central unit for correspondence, and the terminal unit is provided with reservation processing terminal unit 2 having the input section 21, display section 23, and ticket issuing section 25 and control section 27, the seat reservation and required items inputted to the unit 2 are temporarily stored in the register 4, the content of the state of reservation memory unit 6 edited based on the state of reservation stored in the reservation file 36 is referenced, the discrimination unit 10 discriminates the judgement of the central unit to minimize the ineffective call to the central unit, allowing to display it on the reservation state display unit 8.
    • 10. 发明专利
    • SEMICONDUCTOR MEMORY ELEMENT
    • JPS62132297A
    • 1987-06-15
    • JP27110585
    • 1985-12-02
    • HITACHI LTD
    • YAMADA NAOKIMAEHARA TOMOHARU
    • G11C11/401G11C11/34G11C15/00G11C15/04
    • PURPOSE:To retrieve the contents of memory data and to facilitate the access of related information by providing a latch circuit to hold comparing data, plural comparing circuits to divide and compare the data read from a memory cell into plural blocks, an encoder circuit to detect the result and a driving circuit to the output as an address signal. CONSTITUTION:When a memory cell array 51 is composed of 1,024 line X1,024 row by one mega bit, a line address is latched by an address buffer 54, decoded by a row decoder 52 and sent to the memory cell array 51. The 1024 outputs after selecting the memory cell array 51. The 1024 outputs after selecting the line are unified to the 16 bit output group of 64 sets through a sense amplifier part 53. Respective sets are compared in parallel by the comparing address of 15 bits and a comparator 57. The output result is encoded by an encoder 58, latched as the actual address information of 6 bits and sent to the same signal lines I9-I4 as the input address by a bus driver 56.