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1. 发明专利

DE3108568A1 未知
公开(公告)号：DE3108568A1
公开(公告)日：1982-02-04
申请号：DE3108568
申请日：1981-03-06
申请人： HITACHI LTD
发明人： WADA KENICHI , YAMADA NAOKI
IPC分类号： G06F9/22 , G06F9/38 , G06F9/46 , G06F9/48
摘要： An information processing system having an instruction unit for decoding each of successive instructions to generate an address of a next instruction, and additionally, when a branch instruction is decoded, a branch-to address of the decoded branch instruction. An execution unit sequentially executes the decoded instructions and a plurality of registers are provided for storing the next instruction address and the branch-to address. A pointer is generated to indicate one of the registers in which the next instruction address or the branch-to address is to be stored and the pointer is changed sequentially and cyclically in response to a first signal which is generated by the execution unit upon completion of execution of each decoded instruction or a second signal which is generated by the execution unit upon success in branch when a branch instruction is executed. Further provided is a delay circuit for receiving the pointer and generating it at a predetermined time delay. The delayed pointer is latched at a timing predetermined by the first and second signals and an interrupt signal produced, upon detection of an interrupt request, at a timing determined in dependence on the type of the interrupt request, and the instruction address used for a program status word is read out of one of the registers indicted by the latched pointer.

2. 发明专利

DE2918357A1 未知
公开(公告)号：DE2918357A1
公开(公告)日：1979-11-15
申请号：DE2918357
申请日：1979-05-07
申请人： HITACHI LTD
发明人： YAMADA NAOKI , WADA KENICHI
IPC分类号： G06F9/30 , G06F9/38 , G06F11/14 , G06F13/16 , G06F13/06 , G11C9/00 , G06F11/00
摘要： A data processing system using a store data buffer control device includes plural store data buffers and the data from a processor is temporarily stored in the store data buffers and then transferred to a memory. A shift register is used to trace the storing requests from the processor so that the storing requests re-executable in the instruction re-execution taking place at the time of a fault occurring are distinguished from the storing requests not re-executable in the same operation. The data held in the store data buffers corresponding to the re-executable requests is invalidated while the data held in the store data buffers corresponding to the non-re-executable requests is kept valid.

3. 发明专利

JPH09320288A NONVOLATILE MEMORY 失效
公开(公告)号：JPH09320288A
公开(公告)日：1997-12-12
申请号：JP16072396
申请日：1996-05-31
申请人： HITACHI LTD , MITSUBISHI ELECTRIC CORP
发明人： YAMADA NAOKI , OSHIMA KAZUYOSHI , OBA ATSUSHI
IPC分类号： G11C17/00 , G11C11/407 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile memory provided with a charge pump circuit which can form highly accurate internal operation voltage. SOLUTION: Absolutely low pre-charge voltage is formed for a prescribed output voltage by a first charge pump circuit, made to have comparatively large current-supplying capability, and output voltage is quickly raised to a half voltage by a pre-charge circuit consisting of switches. The operation of a second charge pump made to have comparatively small current supplying capability is controlled, to obtain the prescribed output voltage, while switches constituting the pre-charge circuit are made an off state, when the output voltage reaches the pre-charge voltage.

4. 发明专利

JPH0749838A METHOD FOR REFERRING TO AND MAINTAINING USER SHARING LIBRARY DATA 失效
公开(公告)号：JPH0749838A
公开(公告)日：1995-02-21
申请号：JP19660193
申请日：1993-08-09
申请人： HITACHI LTD
发明人： YAMADA NAOKI , OKAE MASAHIRO
IPC分类号： G06F9/06 , G06F15/00
摘要： PURPOSE:To make the nonstop revision of the library data possible that many users use by a time sharing system. CONSTITUTION:Two physical libraries 11 and 12 where data exist are prepared and a virtual library 10 where no data exits is defined. The virtual library 10 is made to correspond to one of the physical libraries 11 and 12 and managed with a table 22. The users 1-4 when reading out library data specify the virtual library 10. An OS registers correspondence information on the virtual and physical libraries in a user profile 21 with the table 22 and reads out data of the physical library 12. The user 1 serves even as a maintenance supervisor, performs updating operation by using the physical library 11 not in correspondence relation with the virtual library 10, and updates the table 22 with a TSS command 32 after the completion of the updating operation.

5. 发明专利

JPS6375949A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6375949A
公开(公告)日：1988-04-06
申请号：JP21953986
申请日：1986-09-19
申请人： HITACHI LTD
发明人： YAMADA NAOKI , NAKAMURA SHINICHI
IPC分类号： G06F9/34 , G06F12/06
摘要： PURPOSE:To easily realize the transfer of address conversion to anther area, by mapping the address conversion applied on instruction readout, and the address conversion applied on data access, separately in different memory areas. CONSTITUTION:An instruction readout address expanding information holding register is sent out to an address conversion mechanism 7 when a processor performs instruction readout access on an overlay area 11, and is operated to obtain a main memory address. Similarly, an operand readout address expanding information holding register is sent out to the address conversion mechanism 7 when the processor 3 performs operand readout access, and is operated to obtain the address of the main memory 4. In such a way, it is possible to handle data in another main memory area by a control program by supplying different expanding information, and also to operate a system assuming the overlay area 11 as an even program area by coinciding the expanding information.

6. 发明专利

JPS6032215B2 失效
公开(公告)号：JPS6032215B2
公开(公告)日：1985-07-26
申请号：JP628479
申请日：1979-01-22
申请人： HITACHI LTD
发明人： YAMADA NAOKI
IPC分类号： G06F11/22 , G01R31/3183 , G06F1/04 , G06F11/00

7. 发明专利

JPS5956278A Data processing device 失效
标题翻译：数据处理设备
公开(公告)号：JPS5956278A
公开(公告)日：1984-03-31
申请号：JP16651082
申请日：1982-09-27
申请人： Hitachi Ltd
发明人： YAMADA NAOKI
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/08
摘要： PURPOSE:To shorten the time from instruction read to operand read to improve the performance of a processing device, by providing an adder, which outputs a logical address, and a generating means which combines the output of an address conversion mechanism and a lower bit part of the logical address to generate the whole of an actual address. CONSTITUTION:When the value of a base register number 2 of an instruction set to an instruction register 1 is (1) and the value of an address displacement 3 is 900 in the hexadecimal numeration, contents of the base register number 2 are transmitted to a general register 4 and a high-speed address conversion buffer 11, and contents of a base register and an actual address value are read out. Since it cannot be discriminated at this time whether the actual address value is 00008 or 00009, both values are outputted. The value of the general register 4 is inputted to an address adder 5 to perform address addition. The value of a carry of upper 20 bits of the address is transmitted to the high-speed address conversion buffer 11 in the course of address addition, and value 00008 for the carry is selected as the actual address by a selecting circuit 14.
摘要翻译：目的：通过提供输出逻辑地址的加法器和将地址转换机构的输出与低位部分组合的发生装置缩短从指令读取到操作数读取的时间，以提高处理装置的性能的逻辑地址来生成整个实际地址。构成：当指令寄存器1的指令的基址寄存器编号2的值为（1），并且地址位移3的值在十六进制数字中为900时，基地址寄存器编号2的内容被发送到通用寄存器4和高速地址转换缓冲器11，读出基本寄存器和实际地址值的内容。由于此时无法辨别实际地址值是00008还是00009，所以输出两个值。通用寄存器4的值被输入到地址加法器5以执行地址相加。在地址相加过程中，将地址高20位的进位值发送到高速地址转换缓冲器11，并通过选择电路14将进位的值00008选择为实际地址。

8. 发明专利

JPS5831527B2 失效
公开(公告)号：JPS5831527B2
公开(公告)日：1983-07-06
申请号：JP1790475
申请日：1975-02-14
申请人： HITACHI LTD
发明人： KATO MASAO , YAMADA NAOKI , KONO KATSUYA
IPC分类号： G01D21/00 , G06F11/22 , G08C25/00

9. 发明专利

JPS5815813B2 失效
公开(公告)号：JPS5815813B2
公开(公告)日：1983-03-28
申请号：JP9026875
申请日：1975-07-25
申请人： HITACHI LTD
发明人： YAMADA NAOKI
IPC分类号： G06F12/08 , G06F9/52 , G06F12/00 , G06F13/00 , G06F15/16 , G06F15/177

10. 发明专利

JPS5848129A DATA PROCESSOR 失效
公开(公告)号：JPS5848129A
公开(公告)日：1983-03-22
申请号：JP14625181
申请日：1981-09-18
申请人： HITACHI LTD
发明人： YAMADA NAOKI , IZUMI CHIKAHIKO
IPC分类号： G06F11/22 , G06F11/267 , G06F13/00
摘要： PURPOSE:To find design inferiority in a parity check by an input and output processor through pseudo input an output equipment which sends out an interface check signal for showing parity check incongruence when an interface determination signal is turned off. CONSTITUTION:Interface signals 511-51N are sent to an input and output processor and also inputted to a parity check signal generating circuit 11. The output of the cirucit 11 is inputted to an exclusive OR circuit 12 to output an interface check signal 52. The exclusive OR circuit 12 inputs the output of an interface determination signal 53 through a signal NOT circuit 13 to invert the value of the interface parity check signal 52 when the signal 53 is turned off, and thus the result of the interface signal parity check shows incongruence in principle, thereby showing the congruency of the parity check result with extremely low probability.

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