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1. 发明授权

US06967133B2 Method for fabricating a semiconductor structure 失效
标题翻译：半导体结构的制造方法
公开(公告)号：US06967133B2
公开(公告)日：2005-11-22
申请号：US10696159
申请日：2003-10-29
申请人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
发明人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10888 , H01L21/26586 , H01L21/28512 , H01L29/66659
摘要： The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
摘要翻译：本发明提供了一种在半导体衬底（10）上制造具有多个栅极堆叠（GS 1，GS 2，GS 3，GS 4）的半导体结构的方法，具有以下步骤：施加栅极堆叠（GS 1，GS 2，GS 3，GS 4）连接到半导体衬底（10）上方的栅极电介质（11）; 在栅堆叠（GS 1，GS 2，GS 3，GS 4）的侧壁上形成侧壁氧化物（17）; 半导体结构上的掩模（12）的应用和图案化; 以及在未被掩模（12）覆盖的区域中相对于栅极堆叠（GS1，GS2）的侧壁氧化物（17）以自对准的方式注入接触掺杂（13）。

2. 发明授权

US07259060B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07259060B2
公开(公告)日：2007-08-21
申请号：US10995677
申请日：2004-11-23
申请人： Jürgen Amon , Jürgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Müller , Dirk Offenberg , Thomas Schuster
发明人： Jürgen Amon , Jürgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Müller , Dirk Offenberg , Thomas Schuster
IPC分类号： H01L21/8242
CPC分类号： H01L21/26586 , H01L27/10861 , H01L27/10873 , H01L27/10888
摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
摘要翻译：一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。选择晶体管具有第二导电类型的相应的第一和第二有源区。第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

3. 发明授权

US07326985B2 Method for fabricating metallic bit-line contacts 失效
标题翻译：金属位线触点的制造方法
公开(公告)号：US07326985B2
公开(公告)日：2008-02-05
申请号：US10692024
申请日：2003-10-23
申请人： Ralf Staub , Jürgen Amon , Norbert Urbansky
发明人： Ralf Staub , Jürgen Amon , Norbert Urbansky
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76807 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L27/10829 , H01L27/10885 , H01L27/10888 , H01L27/10894 , Y10S257/905
摘要： A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
摘要翻译：提供了一种存储单元及其形成方法。为了在半导体晶片上的动态存储单元的位线和选择晶体管之间进行接触，接触孔填充有金属或金属合金。可以在半导体衬底和金属填充物之间引入衬里层。半导体衬底在接触孔中具有掺杂区域。

4. 发明授权

US07473953B2 Method for fabricating metallic bit-line contacts 有权
标题翻译：金属位线触点的制造方法
公开(公告)号：US07473953B2
公开(公告)日：2009-01-06
申请号：US11929215
申请日：2007-10-30
申请人： Ralf Staub , Jürgen Amon , Norbert Urbansky
发明人： Ralf Staub , Jürgen Amon , Norbert Urbansky
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76807 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L27/10829 , H01L27/10885 , H01L27/10888 , H01L27/10894 , Y10S257/905
摘要： A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.
摘要翻译：提供了一种存储单元及其形成方法。为了在半导体晶片上的动态存储单元的位线和选择晶体管之间进行接触，接触孔填充有金属或金属合金。可以在半导体衬底和金属填充物之间引入衬里层。半导体衬底在接触孔中具有掺杂区域。

5. 发明授权

US06368940B1 Method for fabricating a microelectronic structure 有权
标题翻译：微电子结构的制造方法
公开(公告)号：US06368940B1
公开(公告)日：2002-04-09
申请号：US09642325
申请日：2000-08-21
申请人： Jürgen Amon , Albrecht Kieslich
发明人： Jürgen Amon , Albrecht Kieslich
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.
摘要翻译：微电子结构的制造方法包括至少在半导体衬底的主区域的区域中将氮注入到具有沟槽的半导体衬底中。该植入旨在以这样一种方式进行，使得主要区域的氮浓度明显大于沟槽的侧壁处的氮浓度。结果，在随后氧化半导体衬底期间，与侧壁相比，可以在主区域上形成更薄的氧化物层。氧化物层在主区域和侧壁之间的边缘区域中具有均匀的过渡。在半导体衬底的氧化之前将氮掺杂导致主区域上的均匀的氧化物层厚度。

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