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1. 发明授权

US07259060B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07259060B2
公开(公告)日：2007-08-21
申请号：US10995677
申请日：2004-11-23
申请人： Jürgen Amon , Jürgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Müller , Dirk Offenberg , Thomas Schuster
发明人： Jürgen Amon , Jürgen Faul , Johann Alsmeier , Matthias Goldbach , Albrecht Kieslich , Ralf Müller , Dirk Offenberg , Thomas Schuster
IPC分类号： H01L21/8242
CPC分类号： H01L21/26586 , H01L27/10861 , H01L27/10873 , H01L27/10888
摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
摘要翻译：一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。选择晶体管具有第二导电类型的相应的第一和第二有源区。第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

2. 发明授权

US06967133B2 Method for fabricating a semiconductor structure 失效
标题翻译：半导体结构的制造方法
公开(公告)号：US06967133B2
公开(公告)日：2005-11-22
申请号：US10696159
申请日：2003-10-29
申请人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
发明人： Jürgen Amon , Jürgen Faul , Ulrike Gruening , Frank Jakubowski , Thomas Schuster , Rudolf Strasser
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10888 , H01L21/26586 , H01L21/28512 , H01L29/66659
摘要： The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).
摘要翻译：本发明提供了一种在半导体衬底（10）上制造具有多个栅极堆叠（GS 1，GS 2，GS 3，GS 4）的半导体结构的方法，具有以下步骤：施加栅极堆叠（GS 1，GS 2，GS 3，GS 4）连接到半导体衬底（10）上方的栅极电介质（11）; 在栅堆叠（GS 1，GS 2，GS 3，GS 4）的侧壁上形成侧壁氧化物（17）; 半导体结构上的掩模（12）的应用和图案化; 以及在未被掩模（12）覆盖的区域中相对于栅极堆叠（GS1，GS2）的侧壁氧化物（17）以自对准的方式注入接触掺杂（13）。

3. 发明授权

US06943116B2 Method for fabricating a p-channel field-effect transistor on a semiconductor substrate 失效
标题翻译：在半导体衬底上制造p沟道场效应晶体管的方法
公开(公告)号：US06943116B2
公开(公告)日：2005-09-13
申请号：US10372989
申请日：2003-02-24
申请人： Johann Alsmeier , Jürgen Faul
发明人： Johann Alsmeier , Jürgen Faul
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/78 , H01L21/302
CPC分类号： H01L29/4916 , H01L21/823842 , H01L29/7838 , Y10S438/91 , Y10S438/918 , Y10S438/919
摘要： A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.
摘要翻译：在半导体衬底上形成p沟道场效应晶体管。晶体管具有n掺杂栅电极，掩埋沟道，p掺杂源和p掺杂漏极。晶体管的制造方法是，在用于限定n型阱的注入之后，执行氧化以形成栅氧化层，随后沉积n掺杂多晶硅。后者在原位或通过专用注入步骤掺杂硼或氟化硼颗粒。在热处理中，硼受体穿过氧化物层进入n型阱的衬底，其中它们形成p掺杂区，用于反掺杂并设置阈值电压。这导致一个陡峭的轮廓，允许一个浅埋的通道。穿过氧化物层的数量颗粒的控制通过在N 2 O 2气氛中氮化氧化物层来实现。

4. 发明授权

US06509599B1 Trench capacitor with insulation collar and method for producing the trench capacitor 有权
标题翻译：具有绝缘环的沟槽电容器和用于生产沟槽电容器的方法
公开(公告)号：US06509599B1
公开(公告)日：2003-01-21
申请号：US09232081
申请日：1999-01-15
申请人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
发明人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact.
摘要翻译：特别是在半导体存储单元中使用的沟槽电容器具有形成在衬底中的沟槽; 形成在所述沟槽的上部区域中的绝缘套环; 在作为第一电容器板的基板区域中的可选掩埋板; 衬在沟槽的下部区域的绝缘层和作为电容器电介质的绝缘套管; 作为第二电容器板填充到所述沟槽中的导电的第二填充材料; 以及在衬底的表面下方的埋入接触。衬底在其掩埋接触区域的表面下方具有通过注入，等离子体掺杂和/或气相沉积引入的掺杂区域。隧道层，特别是氧化物，氮化物或氮氧化物层优选形成在埋入触点的界面处。

5. 发明授权

US07078325B2 Process for producing a doped semiconductor substrate 失效
公开(公告)号：US07078325B2
公开(公告)日：2006-07-18
申请号：US09904360
申请日：2001-07-12
申请人： Giuseppe Curello , Jürgen Faul
发明人： Giuseppe Curello , Jürgen Faul
IPC分类号： H01L21/22
CPC分类号： H01L21/02667 , H01L21/2022 , H01L21/74 , H01L21/823807 , H01L21/823892 , H01L29/365
摘要： A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.

6. 发明授权

US06828191B1 Trench capacitor with an insulation collar and method for producing a trench capacitor 失效
标题翻译：具有绝缘环的沟槽电容器和用于制造沟槽电容器的方法
公开(公告)号：US06828191B1
公开(公告)日：2004-12-07
申请号：US09363277
申请日：1999-07-28
申请人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
发明人： Kai Wurster , Martin Schrems , Jürgen Faul , Klaus-Dieter Morhard , Alexandra Lamprecht , Odile Dequiedt
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.
摘要翻译：特别是在半导体存储单元中使用的沟槽电容器具有形成在衬底中的沟槽; 形成在所述沟槽的上部区域中的绝缘套环; 在作为第一电容器板的基板区域中的可选掩埋板; 衬在沟槽的下部区域的绝缘层和作为电容器电介质的绝缘套管; 作为第二电容器板填充到所述沟槽中的导电的第二填充材料; 以及在衬底的表面下方的埋入接触。衬底在其掩埋接触区域的表面下方具有通过注入，等离子体掺杂和/或气相沉积引入的掺杂区域。隧道层，特别是氧化物，氮化物或氮氧化物层优选形成在埋入触点的界面处。还提供了一种制造沟槽电容器的方法。

7. 发明授权

US06664167B2 Memory with trench capacitor and selection transistor and method for fabricating it 失效
公开(公告)号：US06664167B2
公开(公告)日：2003-12-16
申请号：US10085940
申请日：2002-02-28
申请人： Dietmar Temmler , Herbert Benzinger , Wolfram Karcher , Catharina Pusch , Martin Schrems , Jürgen Faul
发明人： Dietmar Temmler , Herbert Benzinger , Wolfram Karcher , Catharina Pusch , Martin Schrems , Jürgen Faul
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10832
摘要： A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

8. 发明授权

US06326262B1 Method for fabricating epitaxy layer 有权
标题翻译：外延层及其生产方法
公开(公告)号：US06326262B1
公开(公告)日：2001-12-04
申请号：US09651492
申请日：2000-08-30
申请人： Dietmar Temmler , Herbert Benzinger , Wolfram Karcher , Catharina Pusch , Martin Schrems , Jürgen Faul
发明人： Dietmar Temmler , Herbert Benzinger , Wolfram Karcher , Catharina Pusch , Martin Schrems , Jürgen Faul
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L27/10832
摘要： A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at least partly surrounded by the monocrystalline region. An epitaxial layer is grown on the monocrystalline region. The electrically insulating region is at least partly overgrown laterally with the epitaxial layer, thereby forming an epitaxial closing joint above the electrically insulating region due to the overgrowth. The epitaxial layer is at least partly removed above the electrically insulating region, thereby the epitaxial closing joint is at least partly removed.
摘要翻译：一种制造外延层的方法包括提供具有至少部分未覆盖的白杨碱区域的衬底表面的衬底以及与单晶区域相邻并且至少部分被单晶区域包围的至少一个电绝缘区域。在单晶区域上生长外延层。电绝缘区域至少部分地与外延层横向成长，从而由于过度生长而在电绝缘区域上形成外延闭合接头。在电绝缘区域上至少部分去除外延层，从而至少部分去除外延闭合接头。

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