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1. 发明授权

US06674113B2 Trench capacitor and method for manufacturing the same 有权
标题翻译：沟槽电容器及其制造方法
公开(公告)号：US06674113B2
公开(公告)日：2004-01-06
申请号：US10254692
申请日：2002-09-25
申请人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
IPC分类号： H01L2708
CPC分类号： H01L27/10861
摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.
摘要翻译：沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。第一电容器电极具有延伸到基板中的管状结构。第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置之间。

2. 发明授权

US07041568B2 Method for the production of a self-adjusted structure on a semiconductor wafer 失效
标题翻译：在半导体晶片上制造自调整结构的方法
公开(公告)号：US07041568B2
公开(公告)日：2006-05-09
申请号：US10485307
申请日：2002-07-18
申请人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
发明人： Matthias Goldbach , Thomas Hecht , Jörn Lützen , Bernhard Sell
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L21/0274
摘要： A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle Θ of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.
摘要翻译：半导体晶片的层表面上的结构具有至少一个反射用于电磁辐射的第一区域区域（8,9）和至少一个第二基本上不反射区域区域（10,11,12）。在所述层表面上产生透光绝缘层（13）和感光层。将电磁辐射以角度引导到感光层上。入射角和层表面的结构以横向偏移成像到感光层中。

3. 发明授权

US06633061B2 SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method 有权
标题翻译： SOI衬底，形成在SOI衬底中的半导体电路，以及相关联的制造方法
公开(公告)号：US06633061B2
公开(公告)日：2003-10-14
申请号：US09939998
申请日：2001-08-27
申请人： Jörn Lützen , Bernhard Sell
发明人： Jörn Lützen , Bernhard Sell
IPC分类号： H01L27108
CPC分类号： H01L27/10844 , H01L21/762 , H01L27/108
摘要： In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier and a diffusion barrier is used to reliably prevent diffusion of impurities between element layers. This allows semiconductor circuits to be produced with smaller structure sizes and with a higher integration density.
摘要翻译：在SOI衬底中，使用形成在SOI衬底中的半导体电路和相关联的制造方法，具有势垒的阻挡层和扩散阻挡层，以可靠地防止杂质在元件层之间的扩散。这允许以更小的结构尺寸和更高的集成密度来生产半导体电路

4. 发明授权

US06756626B2 Trench capacitor having an insulation collar 失效
标题翻译：具有绝缘环的沟槽电容器
公开(公告)号：US06756626B2
公开(公告)日：2004-06-29
申请号：US09962576
申请日：2001-09-24
申请人： Jörn Lützen
发明人： Jörn Lützen
IPC分类号： H01L27108
CPC分类号： H01L27/1087 , H01L27/10873
摘要： A trench capacitor has a bottle-shaped trench in a semiconductor substrate. The bottle-shaped trench has a wider lower region and a narrower upper region. An outer electrode layer is formed in the semiconductor substrate around a lower section of the wider lower region of the trench. A dielectric intermediate layer is provided on the lower section of the trench wall in the wider lower region of the trench. A first, thick insulation layer, which adjoins the dielectric intermediate layer, is provided on an upper section of the trench wall in the wider lower region of the trench. A second, thin insulation layer, which adjoins the first thick insulation layer, is formed on the trench wall in the narrower upper region of the trench. An inner electrode layer substantially fills the trench. A method of producing a trench capacitor is also provided.
摘要翻译：沟槽电容器在半导体衬底中具有瓶形沟槽。瓶形沟槽具有较宽的下部区域和较窄的上部区域。在沟槽的较宽下部的下部的半导体衬底内形成有外部电极层。电介质中间层设置在沟槽的较宽下部区域的沟槽壁的下部。邻近电介质中间层的第一厚绝缘层设置在沟槽的较宽下部区域中的沟槽壁的上部。邻接第一厚绝缘层的第二薄绝缘层形成在沟槽的较窄上部区域的沟槽壁上。内部电极层基本上填充沟槽。还提供了一种制造沟槽电容器的方法。

5. 发明授权

US07087484B2 Method for fabricating trench capacitors for integrated semiconductor memories 有权
标题翻译：用于制造用于集成半导体存储器的沟槽电容器的方法
公开(公告)号：US07087484B2
公开(公告)日：2006-08-08
申请号：US10616396
申请日：2003-07-09
申请人： Matthias Goldbach , Jörn Lützen , Andreas Orth
发明人： Matthias Goldbach , Jörn Lützen , Andreas Orth
IPC分类号： H01L28/8242
CPC分类号： H01L27/10867 , H01L27/1087
摘要： In a method for fabricating trench capacitors, in particular for memory cells having at least one selection transistor for integrated semiconductor memories, a trench for the trench capacitor is formed. The trench has a lower trench region, in which the capacitor is disposed, and an upper trench region, in which an electrically conductive connection from an electrode of the capacitor to a diffusion zone of the selection transistor is disposed. The method reduces the number of process steps for the fabrication of memory cells and enables fabrication of buried collars in the storage capacitors with an insulation quality as required for the fabrication of very large-scale integrated memory cells (
摘要翻译：在用于制造沟槽电容器的方法中，特别是对于具有用于集成半导体存储器的至少一个选择晶体管的存储器单元，形成用于沟槽电容器的沟槽。沟槽具有设置电容器的下沟槽区域和上沟槽区域，其中设置从电容器的电极到选择晶体管的扩散区域的导电连接。该方法减少了用于制造存储器单元的工艺步骤的数量，并且能够以存储非常大规模的集成存储器单元（<300nm沟槽直径）所需的绝缘品质在存储电容器中制造埋入的套环。

6. 发明授权

US06455369B1 Method for fabricating a trench capacitor 失效
标题翻译：沟槽电容器的制造方法
公开(公告)号：US06455369B1
公开(公告)日：2002-09-24
申请号：US09932902
申请日：2001-08-20
申请人： Matthias Förster , Jörn Lützen , Martin Gutsche , Anja Morgenschweis
发明人： Matthias Förster , Jörn Lützen , Martin Gutsche , Anja Morgenschweis
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L28/84 , Y10S438/964
摘要： A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.
摘要翻译：一种制造沟槽电容器的方法，包括以下步骤：提供硅衬底; 在硅衬底中形成具有下部区域和表面的沟槽; 以及在沟槽的下部区域中的硅衬底中形成掺杂层。此外，在沟槽的下部区域产生具有直径范围为10〜100nm的硅晶粒的粗糙化硅层。将介电中间层施加在粗糙化硅层上，并且沟槽填充有掺杂层。

7. 发明授权

US06919255B2 Semiconductor trench structure 失效
标题翻译：半导体沟槽结构
公开(公告)号：US06919255B2
公开(公告)日：2005-07-19
申请号：US10630373
申请日：2003-07-30
申请人： Albert Birner , Matthias Goldbach , Thomas Hecht , Lars Heineck , Stephan Kudelka , Jörn Lützen , Dirk Manger , Andreas Orth
发明人： Albert Birner , Matthias Goldbach , Thomas Hecht , Lars Heineck , Stephan Kudelka , Jörn Lützen , Dirk Manger , Andreas Orth
IPC分类号： H01L27/108 , H01L21/00 , H01L21/20 , H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.
摘要翻译：一种制造半导体沟槽结构的方法包括在半导体衬底中形成沟槽并用填充物填充沟槽。具有第一最高温度的第一热处理固化填料。从沟槽的上部区域移除填料至达边界表面限定了一个环形区域。在具有不显着高于第一最高温度的第二最高温度的第二热处理中，衬套沉积在套环区域和边界表面上。将衬垫从边界表面移除，从而暴露填料。然后从沟槽的下部区域去除填料。

8. 发明授权

US06939805B2 Method of etching a layer in a trench and method of fabricating a trench capacitor 失效
标题翻译：在沟槽中蚀刻层的方法和制造沟槽电容器的方法
公开(公告)号：US06939805B2
公开(公告)日：2005-09-06
申请号：US10253196
申请日：2002-09-24
申请人： Jörn Lützen , Barbara Schmidt , Stefan Rongen , Martin Schrems , Daniel Köhler
发明人： Jörn Lützen , Barbara Schmidt , Stefan Rongen , Martin Schrems , Daniel Köhler
IPC分类号： C09K13/00 , H01L21/302 , H01L21/3065 , H01L21/461 , H01L21/8242
CPC分类号： H01L27/10861 , H01L21/3065 , H01L27/1087
摘要： To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.
摘要翻译：为了在衬底中制造沟槽电容器，在衬底中形成沟槽。沟槽具有上部区域和下部区域。在沟槽中，在上部区域和下部区域中首先沉积纳米晶体和/或纳米晶体的晶种层。然后，通过蚀刻工艺从沟槽的上部区域去除纳米晶体和/或种子层。选择蚀刻工艺的蚀刻参数，使得在上部区域和下部区域中未被覆盖的种子层和/或纳米晶体仅从上部区域移除。因此，可以在沟槽的下部区域避免昂贵的掩模层。

9. 发明授权

US06853023B2 Semiconductor memory cell configuration and a method for producing the configuration 失效
标题翻译：半导体存储单元配置及其制造方法
公开(公告)号：US06853023B2
公开(公告)日：2005-02-08
申请号：US10356780
申请日：2003-01-31
申请人： Bernd Goebel , Jörn Lützen , Martin Popp , Harald Seidl
发明人： Bernd Goebel , Jörn Lützen , Martin Popp , Harald Seidl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864
摘要： A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.
摘要翻译：半导体存储单元配置包括分别具有沟槽电容器和垂直选择晶体管的动态存储器单元，存储单元以矩阵形式布置，沟槽电容器和相关联的垂直选择晶体管在每种情况下彼此以行的形式相互依次， /或列。

10. 发明授权

US06977405B2 Semiconductor memory with memory cells comprising a vertical selection transistor and method for fabricating it 失效
标题翻译：具有包括垂直选择晶体管的存储单元的半导体存储器及其制造方法
公开(公告)号：US06977405B2
公开(公告)日：2005-12-20
申请号：US10792742
申请日：2004-03-05
申请人： Jörn Lützen , Bernd Goebel , Dirk Schumann , Martin Gutsche , Harald Seidl , Martin Popp , Alfred Kersch , Werner Steinhögl
发明人： Jörn Lützen , Bernd Goebel , Dirk Schumann , Martin Gutsche , Harald Seidl , Martin Popp , Alfred Kersch , Werner Steinhögl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10891
摘要： In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.
摘要翻译：为了制造半导体存储器，在第一沟槽中布置有沟槽电容器。在第一沟槽的旁边，在衬底中布置有第一纵向沟槽，并且在第一沟槽的另一侧平行的第二纵向沟槽。第一间隔字线布置在第一纵向沟槽中，第二间隔字线布置在第二纵向沟槽中。布置在第一沟槽中，连接腹板之间的第一隔离物字线和第二隔离物字线之间的厚度，该厚度在第一隔离物字线的方向上小于第一沟槽的方向上的宽度的一半的第一个间隔字线。

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