会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Dual supply level shifter circuits
    • 双电源电平转换电路
    • US08970285B2
    • 2015-03-03
    • US13831828
    • 2013-03-15
    • John M. PigottIra G. MillerPaul E. Fletcher
    • John M. PigottIra G. MillerPaul E. Fletcher
    • H03L5/00
    • H03K19/018528H03K19/018521
    • A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage.
    • 双电源电平移位器电路包括开关电路和耦合到开关电路的一组电平移位器电路。 开关电路包括第一组耦合的晶体管,其中电源开关电路耦合到第一电源,该第一电源被配置为提供第一电源电压并被耦合到第二电源,该第二电源被配置为提供第二电源 电压。 该组电平移位器电路包括第二组耦合晶体管,其中该组电平移位器电路被配置为从第一电路接收输入节点处的电压输入信号并提供给双电源电平移位器的输出节点 对具有第一电源电压和第二电源电压之间的最高电压值的值的输出信号进行电路化。
    • 4. 发明申请
    • DUAL SUPPLY LEVEL SHIFTER CIRCUITS
    • 双电源电平更换电路
    • US20140266385A1
    • 2014-09-18
    • US13831828
    • 2013-03-15
    • John M. PigottIra G. MillerPaul E. Fletcher
    • John M. PigottIra G. MillerPaul E. Fletcher
    • H03L5/00
    • H03K19/018528H03K19/018521
    • A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage.
    • 双电源电平移位器电路包括开关电路和耦合到开关电路的一组电平移位器电路。 开关电路包括第一组耦合的晶体管,其中电源开关电路耦合到第一电源,该第一电源被配置为提供第一电源电压并被耦合到第二电源,该第二电源被配置为提供第二电源 电压。 该组电平移位器电路包括第二组耦合晶体管,其中该组电平移位器电路被配置为从第一电路接收输入节点处的电压输入信号并提供给双电源电平移位器的输出节点 对具有第一电源电压和第二电源电压之间的最高电压值的值的输出信号进行电路化。
    • 5. 发明申请
    • CIRCUITRY IN A DRIVER CIRCUIT
    • 驱动电路中的电路
    • US20100271078A1
    • 2010-10-28
    • US12429491
    • 2009-04-24
    • Ira G. MillerJohn M. Pigott
    • Ira G. MillerJohn M. Pigott
    • H03K3/00H03L5/00
    • H03K3/356113H02M1/08H02M3/1588H03K3/0375H03K17/6874H03K2217/0081Y02B70/1466
    • A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.
    • 驱动器电路包括第一和第二电压轨,第一预驱动器电路,功率晶体管,比较电路,其指示第一电压轨的电压电平何时高于或低于参考电压电平;电平移位电路耦合 在提供电平移位输出的第一电压轨和第二电压轨之间,耦合到第一电压轨和第一电路节点的渐缩缓冲电路,其中锥形缓冲电路接收电平移位输出并提供缓冲输出 所述第一预驱动晶体管的控制电极以及耦合在所述第一电路节点和所述第二电压轨之间的轨电压调整电路,所述轨电压调整电路响应于所述比较电路,指示所述第一电压轨的电压高于 参考电压电平,调整第二电压轨的电压电平。
    • 6. 发明授权
    • Circuitry in a driver circuit
    • 电路中的驱动电路
    • US07808286B1
    • 2010-10-05
    • US12429491
    • 2009-04-24
    • Ira G. MillerJohn M. Pigott
    • Ira G. MillerJohn M. Pigott
    • H03K3/00
    • H03K3/356113H02M1/08H02M3/1588H03K3/0375H03K17/6874H03K2217/0081Y02B70/1466
    • A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail.
    • 驱动器电路包括第一和第二电压轨,第一预驱动器电路,功率晶体管,比较电路,其指示第一电压轨的电压电平何时高于或低于参考电压电平;电平移位电路耦合 在提供电平移位输出的第一电压轨和第二电压轨之间,耦合到第一电压轨和第一电路节点的渐缩缓冲电路,其中锥形缓冲电路接收电平移位输出并提供缓冲输出 所述第一预驱动晶体管的控制电极以及耦合在所述第一电路节点和所述第二电压轨之间的轨电压调整电路,所述轨电压调整电路响应于所述比较电路,指示所述第一电压轨的电压高于 参考电压电平,调整第二电压轨的电压电平。
    • 8. 发明申请
    • DUAL-LOOP DC-TO-DC CONVERTER APPARATUS
    • 双环路DC-DC转换器装置
    • US20100079126A1
    • 2010-04-01
    • US12242145
    • 2008-09-30
    • John M. Pigott
    • John M. Pigott
    • G05F1/565
    • H02M3/156H02M2001/0016
    • A dual loop DC-to-DC converter is provided that includes a first control loop that maintains a DC output voltage (VOUT) less than or equal to a desired maximum value of the VOUT, a second control loop that operates simultaneously with the first control loop and maintains a DC input voltage (VIN) greater than or equal to a desired minimum value of the VIN, and a duty cycle selection module. The first control loop generates a first clock signal having a first duty cycle, and the second control loop generates a second clock signal having a second duty cycle. The duty cycle selection module continuously determines which one of the first duty cycle and the second duty cycle has a lower duty cycle value, and continuously generates a PWM output signal having a modulated duty cycle equal to the lower duty cycle value.
    • 提供一种双回路DC-DC转换器,其包括第一控制回路,其保持小于或等于VOUT的期望最大值的DC输出电压(VOUT);与第一控制同时操作的第二控制回路 并且保持大于或等于VIN的期望最小值的DC输入电压(VIN)和占空比选择模块。 第一控制环路产生具有第一占空比的第一时钟信号,而第二控制环路产生具有第二占空比的第二时钟信号。 占空比选择模块连续地确定第一占空比和第二占空比中的哪一个具有较低的占空比值,并连续产生具有等于较低占空比值的调制占空比的PWM输出信号。
    • 9. 发明申请
    • APPARATUS FOR OPTIMIZING DIODE CONDUCTION TIME DURING A DEADTIME INTERVAL
    • 用于在死亡间隔期间优化二极管导通时间的装置
    • US20080278125A1
    • 2008-11-13
    • US11747360
    • 2007-05-11
    • John M. Pigott
    • John M. Pigott
    • G05F1/40
    • H02M3/1588H02M1/38Y02B70/1466
    • Deadtime optimization techniques and circuits are provided which implement closed loop feedback to reduce a duration of a deadtime interval by reducing a diode conduction time (DCT) to an optimized or minimized value. Information regarding DCT is fed back to continuously adjust the relative delay between a first driver path which drives a first transistor and a second driver path which drives a second transistor. For instance, information regarding DCT can be measured and stored, and then used to generate a control signal which continuously adjusts (e.g., increases or decreases) a variable delay associated with a delay element in one of the driver paths of one of the transistors. The delay is adjusted to a value which drives the DCT towards an optimum value. By continuously changing the relative delay between the first driver path and the second driver path, the DCT can be driven to an optimum value
    • 提供了死区优化技术和电路,其实现闭环反馈以通过将二极管导通时间(DCT)减小到优化或最小化的值来减少死区间隔的持续时间。 反馈关于DCT的信息,以连续地调节驱动第一晶体管的第一驱动路径和驱动第二晶体管的第二驱动路径之间的相对延迟。 例如,可以测量和存储关于DCT的信息,然后用于产生一个控制信号,该控制信号连续调整(例如,增加或减少)与其中一个晶体管之一的驱动器路径中的延迟元件相关联的可变延迟。 将延迟调整为将DCT驱动到最佳值的值。 通过连续地改变第一驱动路径和第二驱动路径之间的相对延迟,可以将DCT驱动到最佳值