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1. 发明申请

WO2012040723A2 APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES 审中-公开
标题翻译：用于实施微页表的装置，方法和系统
公开(公告)号：WO2012040723A2
公开(公告)日：2012-03-29
申请号：PCT/US2011/053306
申请日：2011-09-26
申请人： INTEL CORPORATION , HINTON, Glenn , RAMANUJAN, Raj , CAPE, Scott J. , PARTHASARATHY, Madhavan , ZIMMERMAN, David , DOWNER, Wayne A. , PARTHASARATHY, Rajesh , SMITH, Larry O. , CHAPPELL, Robert S. , SWAMINATHAN, Muthukumar , MOGA, Adrian C.
发明人： HINTON, Glenn , RAMANUJAN, Raj , CAPE, Scott J. , PARTHASARATHY, Madhavan , ZIMMERMAN, David , DOWNER, Wayne A. , PARTHASARATHY, Rajesh , SMITH, Larry O. , CHAPPELL, Robert S. , SWAMINATHAN, Muthukumar , MOGA, Adrian C.
IPC分类号： G06F12/00 , G06F9/06 , G06F13/14
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.
摘要翻译：公开了一种装置，方法，机器可读介质和系统。在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页的存储器页请求的逻辑。该装置还包括能够存储一个或多个存储器页面地址转换的转换后备缓冲器（TLB）。另外，该装置还具有能够响应于TLB未存储由存储器页面请求所引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表格中执行微物理地址查找的页面未命中处理器。该装置还包括能够管理页面未命中处理器标签表项的存储器管理逻辑。微页表引擎允许TLB成为代理，用于确定两级存储器层级中的数据是处于内存的热区还是处于内存的寒冷区域。当数据处于内存冷区时，微页表引擎将数据提取到热内存，然后将热内存块推送到冷内存区。

2. 发明申请

WO2018063706A1 SYSTEM AND METHOD FOR REPLACEMENT IN ASSOCIATIVE MEMORIES USING WEIGHTED PLRU TREES 审中-公开
标题翻译：使用加权PLRU树替换关联存储器的系统和方法
公开(公告)号：WO2018063706A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049341
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： ZHANG, Chunhui , CHAPPELL, Robert S. , ILIN, Yury N.
IPC分类号： G06F12/12
CPC分类号： G06N7/005 , G06F12/0864 , G06F12/12 , G06F12/128 , G06F2212/1016 , G06F2212/1041 , G06F2212/70
摘要： A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node indicator whose value determines the side of the tree structure to which a next memory element replacement operation is directed, and circuitry to cause, responsive to a miss in the associative memory while the decision node indicator points to the minority side of the tree structure, the decision node indicator to point a majority side of the tree structure, and to determine, responsive to a miss while the decision node indicator points to the majority side of the tree structure, whether or not to cause the decision node indicator to point to the minority side of the tree structure, the determination being dependent on a current replacement weight value. The replacement weight value may be counter-based or a probabilistic weight value.
摘要翻译：处理器包括包含以非对称树结构组织的路的关联存储器，包括决策节点指示符的替换控制单元，其值确定下一个存储元件替换操作所针对的树结构的边指令和电路，用于在判决节点指示符指向树结构的少数侧时响应于关联存储器中的未命中而导致决策节点指示符指向树结构的多数侧，并且响应于当决策节点指示符指向树结构的多数侧时，确定是否使决策节点指示符指向树结构的少数侧，确定取决于当前替换权重值。替换权重值可以是基于计数的或概率权重值。

3. 发明申请

WO2013095576A1 PROCESSOR-BASED APPARATUS AND METHOD FOR PROCESSING BIT STREAMS 审中-公开
标题翻译：基于处理器的设备和处理位流的方法
公开(公告)号：WO2013095576A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067036
申请日：2011-12-22
申请人： INTEL CORPORATION , GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , OZTURK, Erdinc , FEGHALI, Wajdi K. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G. , CHAPPELL, Robert S.
发明人： GOPAL, Vinodh , GUILFORD, James D. , WOLRICH, Gilbert M. , OZTURK, Erdinc , FEGHALI, Wajdi K. , YAP, Kirk S. , GULLEY, Sean M. , DIXON, Martin G. , CHAPPELL, Robert S.
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/34
摘要： An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.
摘要翻译：描述了一种用于使用面向位的指令来处理比特流的装置和方法。例如，根据一个实施例的方法包括以下操作：执行用于获得用于操作的比特的指令，所述指令标识起始比特地址和要检索的比特数; 从面向比特的寄存器或高速缓存中检索由起始位地址和位数标识的位; 并对所检索的位执行指定位操作的序列以产生结果。

4. 发明申请

WO2014004234A1 HYBRID CACHE STATE AND FILTER TRACKING OF MEMORY OPERATIONS DURING A TRANSACTION 审中-公开
标题翻译：混合高速缓存状态和过滤器跟踪在交易期间的内存操作
公开(公告)号：WO2014004234A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046709
申请日：2013-06-20
申请人： INTEL CORPORATION
发明人： CHAPPELL, Robert S. , RAJWAR, Ravi , ZHANG, Zhongying , BESSETTE, Jason A.
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/467 , G06F12/0897
摘要： In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，高速缓存存储器可以存储多条高速缓存线，每条高速缓存行包括写入字段以存储写入指示符，以指示在事务性存储器的事务期间是否已经推测写入数据，以及读取集字段以存储多个读取设置指示符，每个指示符指示相应的线程在交易已经提交之前是否已经读取数据。与高速缓冲存储器相关联的压缩过滤器包括第一过滤器存储器，用于在事务已经提交之前存储由第一线程线程读取的高速缓存行的高速缓存行地址的表示。描述和要求保护其他实施例。

5. 发明申请

WO2013115818A1 A METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：用于交互式分析控制指令的方法，装置和系统
公开(公告)号：WO2013115818A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023611
申请日：2012-02-02
申请人： INTEL CORPORATION , RAJWAR, Ravi , DIXON, Martin G. , LAI, Konrad K. , FARCY, Alexandre J. , TOLL, Bret L. , CHAPPELL, Robert S. , MERTEN, Matthew C. , PARTHASARATHY, Rajesh S. , HAMMARLUND, Per
发明人： RAJWAR, Ravi , DIXON, Martin G. , LAI, Konrad K. , FARCY, Alexandre J. , TOLL, Bret L. , CHAPPELL, Robert S. , MERTEN, Matthew C. , PARTHASARATHY, Rajesh S. , HAMMARLUND, Per
IPC分类号： G06F9/30 , G06F9/305
CPC分类号： G06F9/30181 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3851 , G06F9/3859
摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similary provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.
摘要翻译：这里描述了一种用于提供猜测控制指令的装置和方法。提供xAcquire和xRelease指令来定义关键部分。在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。此外，xBegin和xEnd在指令集架构（ISA）中提供了类似的方式来定义事务代码区域。此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

6. 发明申请

WO2018111228A1 APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2018111228A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066242
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

7. 发明申请

WO2018004974A1 PROCESSORS, METHODS, AND SYSTEMS TO IDENTIFY STORES THAT CAUSE REMOTE TRANSACTIONAL EXECUTION ABORTS 审中-公开
标题翻译：处理器，方法和系统来识别造成远程交易执行的仓库
公开(公告)号：WO2018004974A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/035436
申请日：2017-06-01
申请人： INTEL CORPORATION
发明人： KLEEN, Andreas , SADE, Raanan , YASIN, Ahmad , RAJWAR, Ravi , CHAPPELL, Robert S. , DEMENTIEV, Roman
IPC分类号： G06F11/30
CPC分类号： G06F9/30043 , G06F3/0619 , G06F3/0653 , G06F3/0656 , G06F3/0673 , G06F9/3004 , G06F9/30145 , G06F9/3834 , G06F11/30 , G06F12/0815 , G06F12/084
摘要： A method of analyzing aborts of transactional execution transactions. Starting a transactional execution transaction with a first logical processor. Performing, with a second logical processor, store to memory instructions, while the first logical processor is performing the transactional execution transaction. Capturing memory addresses of, and instruction pointer values associated with, at least a sample of the store to memory instructions. Performing, with the second logical processor, a first store to memory instruction to a first memory address, which is to cause the transactional execution transaction to abort. Capturing the first memory address. Determining an instruction pointer value associated with the first store to memory instruction by correlating at least the captured first memory address with the captured memory addresses of said at least the sample of the store to memory instructions.
摘要翻译：
一种分析事务执行事务异常终止的方法。用第一个逻辑处理器开始一个事务执行事务。在第一逻辑处理器正在执行事务执行事务的同时，利用第二逻辑处理器执行对存储器指令的存储。捕获与存储器的至少一个样本相关联的存储器地址和与存储器指令相关联的指令指针值。利用第二逻辑处理器执行对存储器指令的第一存储器指令，该第一存储器指令将导致事务执行事务中止。捕获第一个内存地址。通过将至少所捕获的第一存储器地址与所述至少所述商店样本的所捕获的存储器地址至存储器指令相关联来确定与所述第一存储器至存储器指令相关联的指令指针值。

8. 发明申请

WO2014105151A1 APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
标题翻译：多页翻页预处理缓存器（TLB）的设备和方法
公开(公告)号：WO2014105151A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046910
申请日：2013-06-20
申请人： INTEL CORPORATION , RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
发明人： RAIKIN, Shlomo , HAMAMA, Oren , CHAPPELL, Robert S. , RUST, Camron B. , LUU, Han S. , ONG, Leslie A. , HILDESHEIM, Gur
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02D10/13
摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
摘要翻译：一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

9. 发明申请

WO2014042747A1 CONCURRENT CONTROL FOR A PAGE MISS HANDLER 审中-公开
标题翻译：页面错误处理的并发控制
公开(公告)号：WO2014042747A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/048594
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： HILDESHEIM, Gur , TAN, Chang Kian , CHAPPELL, Robert S. , BHATIA, Rohit
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/1024 , G06F2212/651 , G06F2212/655 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并从寻呼结构获得物理地址的对应部分，与第一步行者同时操作的第二步行者，用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应的线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼缓存中的逻辑。描述和要求保护其他实施例。

10. 发明授权

EP2619675B1 APPARATUS, METHOD, AND SYSTEM FOR IMPLEMENTING MICRO PAGE TABLES 有权
公开(公告)号：EP2619675B1
公开(公告)日：2018-08-22
申请号：EP11827736.7
申请日：2011-09-26
申请人： Intel Corporation
发明人： HINTON, Glenn , RAMANUJAN, Raj , CAPE, Scott J. , PARTHASARATHY, Madhavan , ZIMMERMAN, David , DOWNER, Wayne A. , PARTHASARATHY, Rajesh , SMITH, Larry O. , CHAPPELL, Robert S. , SWAMINATHAN, Muthukumar , MOGA, Adrian C.
IPC分类号： G06F12/1009 , G06F12/1027 , G06F9/06 , G06F12/00 , G06F13/14 , G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F12/06 , G06F12/1009 , G06F2212/1028 , G06F2212/1041 , G06F2212/151 , G06F2212/205 , G06F2212/651 , Y02D10/13
摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

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