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1. 发明申请

WO2002042902A3 METHOD AND APPARATUS FOR SCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR 审中-公开
公开(公告)号：WO2002042902A3
公开(公告)日：2002-05-30
申请号：PCT/US2001/051023
申请日：2001-10-18
申请人： INTEL CORPORATION , CARMEAN, Douglas, M. , BOGGS, Darrell, D. , SAGER, David, J. , MCKEEN, Francis, X. , HAMMARLUND, Per , SINGHAL, Ronak
发明人： CARMEAN, Douglas, M. , BOGGS, Darrell, D. , SAGER, David, J. , MCKEEN, Francis, X. , HAMMARLUND, Per , SINGHAL, Ronak
IPC分类号： G06F9/38
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is couple to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

2. 发明申请

WO2014210345A1 PROCESSORS, METHODS, AND SYSTEMS TO ACCESS A SET OF REGISTERS AS EITHER A PLURALITY OF SMALLER REGISTERS OR A COMBINED LARGER REGISTER 审中-公开
标题翻译：处理器，方法和系统访问一组寄存器，无论是大量的小型寄存器还是组合的大型寄存器
公开(公告)号：WO2014210345A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/044389
申请日：2014-06-26
申请人： INTEL CORPORATION
发明人： TOLL, Bret L. , SINGHAL, Ronak , GUY, Buford M. , NAIK, Mishali
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/30192
摘要： A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
摘要翻译：一方面的处理器包括能够存储打包数据的一组寄存器。执行单元与该组寄存器耦合。执行单元响应于指令以至少两种不同的方式访问该组寄存器。至少两种不同的方式包括第一种方式，其中该组寄存器将表示多个N位寄存器。至少两种不同的方式还包括第二种方式，其中该组寄存器将表示至少2N位的单个寄存器。在一个方面，至少2N比特将是至少256比特。

3. 发明申请

WO2014210363A1 MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译：多个寄存器存储器访问指令，处理器，方法和系统
公开(公告)号：WO2014210363A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/044416
申请日：2014-06-26
申请人： INTEL CORPORATION
发明人： HINTON, Glenn , TOLL, Bret , SINGHAL, Ronak
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G11C7/1036 , G06F9/30043 , G06F9/30109 , G06F9/30163
摘要： A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an MxN-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the MxN-bits of the line of memory.
摘要翻译：处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。多寄存器存储器访问指令是指示存储器位置和寄存器。处理器包括与解码单元和N位寄存器耦合的存储器存取单元。存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器存取操作。该操作涉及在包括指定的寄存器的每个N位寄存器中涉及N位数据。该操作还涉及与所指示的存储器位置相对应的MxN位的存储器行的不同相应的N位部分。要在多个寄存器存储器访问操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的MxN位的至少一半。

4. 发明申请

WO2018111228A1 APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2018111228A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066242
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

5. 发明申请

WO2017105758A1 MONITORING THE OPERATION OF A PROCESSOR 审中-公开
标题翻译：监控处理器的运行
公开(公告)号：WO2017105758A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/062575
申请日：2016-11-17
申请人： INTEL CORPORATION
发明人： NEIGER, Gilbert , ANDERSON, Andrew V. , UHLIG, Richard A. , DURHAM, David M. , SINGHAL, Ronak , WU, Xiangbin , KOTTAPALLI, Sailesh
IPC分类号： G06F11/30
CPC分类号： G06F11/3466 , G06F3/0604 , G06F3/0644 , G06F3/0673 , G06F11/3024 , G06F13/24
摘要： Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
摘要翻译：公开了用于监视处理器的操作的发明的实施例。在一个实施例中，系统包括处理器和处理器外部的硬件代理。处理器包括虚拟化逻辑以提供处理器以根模式和非根模式操作。硬件代理是基于由根处理器执行的软件代理收集的跟踪信息来验证处于非根模式的处理器的操作。

6. 发明公开

EP3014419A1 PROCESSORS, METHODS, AND SYSTEMS TO ACCESS A SET OF REGISTERS AS EITHER A PLURALITY OF SMALLER REGISTERS OR A COMBINED LARGER REGISTER 审中-公开
标题翻译：处理器，方法和访问寄存器的任一组几个较小的寄存器的形式或组合BIGGER注册Systems
公开(公告)号：EP3014419A1
公开(公告)日：2016-05-04
申请号：EP14818729.7
申请日：2014-06-26
申请人： Intel Corporation
发明人： TOLL, Bret L. , SINGHAL, Ronak , GUY, Buford M. , NAIK, Mishali
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3016 , G06F9/30192
摘要： A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.
摘要翻译：一个形态的处理器包括一组能够存储压缩数据的寄存器。执行单元耦接于该组寄存器。所述执行单元访问该组寄存器中的至少两种不同的方式响应于指令。所述至少两种不同的方式包括其中该组寄存器是表示N位寄存器的多个A第一种方式。所述至少两种不同的方式，以便包括其中该组寄存器是代表至少2N比特的单个寄存器的第二方式。在一个方面，所述至少2N个位是为至少256位。

7. 发明公开

EP1334426A2 APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS 审中-公开
标题翻译： DEVICE AND METHOD FOR命令重新安排规划
公开(公告)号：EP1334426A2
公开(公告)日：2003-08-13
申请号：EP01986210.1
申请日：2001-10-18
申请人： INTEL CORPORATION
发明人： CARMEAN, Douglas, M. , BOGGS, Darrell, D. , SAGER, David, J. , MCKEEN, Francis, X. , HAMMARLUND, Per , SINGHAL, Ronak
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

8. 发明公开

EP3014418A1 PACKED DATA ELEMENT PREDICATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
标题翻译：处理器适用于预测打包数据元素，方法，系统和指令
公开(公告)号：EP3014418A1
公开(公告)日：2016-05-04
申请号：EP14818406.2
申请日：2014-06-17
申请人： Intel Corporation
发明人： GUY, Buford M. , SINGHAL, Ronak , NAIK, Mishali , TOLL, Bret L.
IPC分类号： G06F9/06 , G06F9/30
摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

10. 发明公开

EP3014416A1 MULTIPLE REGISTER MEMORY ACCESS INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS 审中-公开
标题翻译： SPEICHERZUGRIFFSBEFEHLE，-PROZESSOREN，-VERFAHREN，UND -SYSTEME MIT MEHREREN REGISTERN
公开(公告)号：EP3014416A1
公开(公告)日：2016-05-04
申请号：EP14817022.8
申请日：2014-06-26
申请人： Intel Corporation
发明人： HINTON, Glenn , TOLL, Bret , SINGHAL, Ronak
IPC分类号： G06F9/06 , G06F12/08
CPC分类号： G11C7/1036 , G06F9/30043 , G06F9/30109 , G06F9/30163
摘要： A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an MxN-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the MxN-bits of the line of memory.
摘要翻译：处理器包括N位寄存器和用于接收多寄存器存储器访问指令的解码单元。多个寄存器存储器访问指令是指示存储器位置和寄存器。处理器包括与解码单元和N位寄存器耦合的存储器存取单元。存储器访问单元响应于多个寄存器存储器访问指令执行多个寄存器存储器访问操作。该操作涉及在包括所指示的寄存器的每个N位寄存器中涉及N位数据。操作还涉及对应于所指示的存储器位置的M×N位存储器线的不同对应的N位部分。要在多个寄存器存储器存取操作中涉及的N位寄存器中的N位数据的总位数至少等于存储器行的M×N位的至少一半。

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