专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060258116A1 Shallow trench isolation 失效
标题翻译：浅沟隔离
公开(公告)号：US20060258116A1
公开(公告)日：2006-11-16
申请号：US11485838
申请日：2006-07-12
申请人： Inki Kim , Sang Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Ping , Wan Lee , Choong Chien , Charlie Tay , Chang Lee , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Ping , Wan Lee , Choong Chien , Charlie Tay , Chang Lee , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823462
摘要： A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
摘要翻译：在半导体衬底上形成隔离结构的方法包括使用包括蚀刻剂气体和聚合物形成气体的工艺气体来打开覆盖衬底的衬垫氧化物层的一部分。通过开口步骤曝光的基板的一部分被蚀刻以形成具有第一斜率和第二斜率的沟槽。第一斜坡大于45度，第二坡度小于45度。填充沟槽以形成隔离结构。

2. 发明授权

US07241665B2 Shallow trench isolation 失效
标题翻译：浅沟隔离
公开(公告)号：US07241665B2
公开(公告)日：2007-07-10
申请号：US11485838
申请日：2006-07-12
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823462
摘要： A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
摘要翻译：在半导体衬底上形成隔离结构的方法包括使用包括蚀刻剂气体和聚合物形成气体的工艺气体来打开覆盖衬底的衬垫氧化物层的一部分。通过开口步骤曝光的基板的一部分被蚀刻以形成具有第一斜率和第二斜率的沟槽。第一斜坡大于45度，第二坡度小于45度。填充沟槽以形成隔离结构。

3. 发明授权

US07091104B2 Shallow trench isolation 失效
公开(公告)号：US07091104B2
公开(公告)日：2006-08-15
申请号：US10351472
申请日：2003-01-23
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Gie Lee , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Gie Lee , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823462
摘要： A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.

4. 发明授权

US06284613B1 Method for forming a T-gate for better salicidation 有权
标题翻译：用于形成更好的盐析的T型门的方法
公开(公告)号：US06284613B1
公开(公告)日：2001-09-04
申请号：US09434920
申请日：1999-11-05
申请人： Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep , Ramakrishnan Rajagopal
发明人： Chivukula Subrahmanyam , Yelehanka Ramachandramurthy Pradeep , Ramakrishnan Rajagopal
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/42376 , H01L29/66545 , H01L29/7833 , H01L29/7836
摘要： A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.
摘要翻译：一种用于T栅极和自对准硅化物工艺的方法，其允许窄的底栅宽度低于0.25μm和宽的顶栅宽度以允许在T栅极的顶部上的硅化物栅极接触。在衬底上形成由绝缘材料构成的虚拟栅极。然后，使用伪栅极作为掩模，优选通过将f（I / I）杂质离子注入到衬底中来形成与虚拟栅极相邻的LDD区域。在衬底表面上形成衬垫氧化物层和电介质层。虚拟栅极上的电介质层优选地通过CMP工艺去除。然后我们去除虚拟栅极以形成露出衬底表面的栅极开口。在栅极开口中的衬底表面上形成栅极电介质层。我们在电介质层和栅极开口中的衬底表面上形成多晶硅层。图案化多晶硅层以形成T形栅极。去除电介质层。我们通过离子注入工艺形成与T型栅极相邻的源极/漏极（S / D）区域。在T栅极和衬底之上形成硅化物层，以形成与SID区的硅化物接触和到T栅极的栅极接触。然后我们在T栅极和衬底上形成介电层（ILD）。我们通过介电层形成接触开口以暴露S / D区域和T型栅极。我们与S / D区域和T型门形成联系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式