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1. 发明授权

US07241665B2 Shallow trench isolation 失效
标题翻译：浅沟隔离
公开(公告)号：US07241665B2
公开(公告)日：2007-07-10
申请号：US11485838
申请日：2006-07-12
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823462
摘要： A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.
摘要翻译：在半导体衬底上形成隔离结构的方法包括使用包括蚀刻剂气体和聚合物形成气体的工艺气体来打开覆盖衬底的衬垫氧化物层的一部分。通过开口步骤曝光的基板的一部分被蚀刻以形成具有第一斜率和第二斜率的沟槽。第一斜坡大于45度，第二坡度小于45度。填充沟槽以形成隔离结构。

2. 发明授权

US07091104B2 Shallow trench isolation 失效
公开(公告)号：US07091104B2
公开(公告)日：2006-08-15
申请号：US10351472
申请日：2003-01-23
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Gie Lee , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ch'ng Toh Ghee , Ramakrishnan Rajagopal , Chiew Gie Lee , Wan Gie Lee , Choong Shiau Chien , Charlie Tay , Chang Gi Lee , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823462
摘要： A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.

3. 发明授权

US07259071B2 Semiconductor device with dual gate oxides 失效
标题翻译：具有双栅极氧化物的半导体器件
公开(公告)号：US07259071B2
公开(公告)日：2007-08-21
申请号：US10973852
申请日：2004-10-25
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Zadig Lam , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Zadig Lam , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.
摘要翻译：制造具有第一有源区和第二有源区的半导体器件的方法包括提供在衬底上限定第一有源区的第一和第二隔离结构。第一有源区域使用第一工作电压，而第二有源区域使用不同于第一电压的第二工作电压。形成覆盖第一和第二有源区的氮化物层。形成覆盖氮化物层的氧化物层。去除覆盖在第一有源区上的氧化物层的第一部分以露出氮化物层的第一部分。使用湿蚀刻方法去除氮化物层的暴露的第一部分，同时留下覆盖第二有源区域的氮化物层的第二部分完好无损。此后，在第一有源区上形成具有第一厚度的第一栅极氧化物，第一栅极氧化物具有面对第一隔离结构的第一边缘和面向第二隔离结构的第二边缘。第一边缘与第一隔离结构隔开第一距离。第二边缘与第二隔离结构隔开第二距离。此后，在第二有源区上形成具有第二厚度的第二栅极氧化物，第二厚度不同于第一厚度。

4. 发明授权

US06818514B2 Semiconductor device with dual gate oxides 有权
标题翻译：具有双栅极氧化物的半导体器件
公开(公告)号：US06818514B2
公开(公告)日：2004-11-16
申请号：US10377167
申请日：2003-02-26
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Zadig Lam , Hitomi Watanabe , Naoto Inoue
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Chiew Sin Ping , Wan Gie Lee , Choong Shiau Chien , Zadig Lam , Hitomi Watanabe , Naoto Inoue
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.
摘要翻译：制造具有第一有源区和第二有源区的半导体器件的方法包括提供在衬底上限定第一有源区的第一和第二隔离结构。第一有源区域使用第一工作电压，而第二有源区域使用不同于第一电压的第二工作电压。形成覆盖第一和第二有源区的氮化物层。形成覆盖氮化物层的氧化物层。去除覆盖在第一有源区上的氧化物层的第一部分以露出氮化物层的第一部分。使用湿蚀刻方法去除氮化物层的暴露的第一部分，同时留下覆盖第二有源区域的氮化物层的第二部分完好无损。此后，在第一有源区上形成具有第一厚度的第一栅极氧化物，第一栅极氧化物具有面对第一隔离结构的第一边缘和面向第二隔离结构的第二边缘。第一边缘与第一隔离结构隔开第一距离。第二边缘与第二隔离结构隔开第二距离。此后，在第二有源区上形成具有第二厚度的第二栅极氧化物，第二厚度不同于第一厚度。

5. 发明授权

US06890822B2 Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 有权
公开(公告)号：US06890822B2
公开(公告)日：2005-05-10
申请号：US10367591
申请日：2003-02-13
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.

6. 发明授权

US07208378B2 Semiconductor device having multiple gate oxide layers and method of manufacturing thereof 失效
标题翻译：具有多个栅极氧化物层的半导体器件及其制造方法
公开(公告)号：US07208378B2
公开(公告)日：2007-04-24
申请号：US11126944
申请日：2005-05-10
申请人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
发明人： Inki Kim , Sang Yeon Kim , Min Paek , Ong Boon Teong , Oh Choong Young , Ng Chun Leng , Joung Joon Ho
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.
摘要翻译：制造半导体器件的方法包括在衬底上限定第一电压区域，第二电压区域和第三电压区域。第一，第二和第三电压区域被配置为分别处理彼此不同的第一，第二和第三电压电平。形成覆盖第一，第二和第三电压区域的氮化物层。形成覆盖氮化物层的氧化物层。图案化氧化物层以暴露覆盖第一电压区域的氮化物层的一部分。使用湿蚀刻工艺去除氮化物层的暴露部分。形成覆盖第一电压区域的第一栅极氧化物层。除去覆盖第二和第三电压区域的氧化物层和氮化物层的部分。杂质被选择性地注入到第三电压区域中，同时防止在第二电压区域中提供杂质。覆盖第二电压区域的第二栅极氧化物和覆盖第三电压区域的第三栅极氧化物同时形成。第二栅极氧化物比第三栅极氧化物厚。

7. 发明授权

US07166901B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07166901B2
公开(公告)日：2007-01-23
申请号：US10950828
申请日：2004-09-27
申请人： Naoto Inoue , Hitomi Sakurai , Min Paek , Sang Yeon Kim , In Ki Kim
发明人： Naoto Inoue , Hitomi Sakurai , Min Paek , Sang Yeon Kim , In Ki Kim
IPC分类号： H01L29/00
CPC分类号： H01L27/0921 , H01L21/76237 , H01L21/823814 , H01L21/823878
摘要： A semiconductor device comprises a semiconductor substrate having a high voltage region and a low voltage region, at least a pair of adjacent high voltage MOS transistors disposed on the high voltage region of the semiconductor substrate, and low voltage MOS transistors disposed on the low voltage region of the semiconductor substrate. A first element isolator comprises a first shallow trench disposed on a surface of the low voltage, region of the semiconductor substrate, and a first dielectric embedded in the first shallow trench. A pair of second element isolators comprises two second shallow trenches spaced apart at an interval between a source region or a drain region of the pair of the adjacent high voltage MOS transistors and a source or a drain region of the other of the pair of the adjacent high voltage MOS transistors, and a second dielectric embedded in each of the second shallow trenches. The second shallow trenches are disposed on a surface of the high voltage region of the semiconductor substrate. A channel cut region having a high impurity concentration is disposed on the surface of the substrate between the second shallow trenches.
摘要翻译：半导体器件包括具有高电压区域和低电压区域的半导体衬底，设置在半导体衬底的高电压区域上的至少一对相邻的高压MOS晶体管和设置在低电压区域上的低压MOS晶体管的半导体衬底。第一元件隔离器包括设置在半导体衬底的低电压区域的表面上的第一浅沟槽和嵌入在第一浅沟槽中的第一电介质。一对第二元件隔离器包括在一对相邻高压MOS晶体管的源极区域或漏极区域之间间隔开的两个第二浅沟槽和一对相邻的高压MOS晶体管中的另一个的源极或漏极区域高电压MOS晶体管和嵌入在每个第二浅沟槽中的第二电介质。第二浅沟槽设置在半导体衬底的高压区域的表面上。具有高杂质浓度的沟道切割区域设置在第二浅沟槽之间的衬底表面上。

8. 发明授权

US07152087B2 Finite impulse response filter 有权
公开(公告)号：US07152087B2
公开(公告)日：2006-12-19
申请号：US10322978
申请日：2002-12-18
申请人： Jong In Choi , Sang Yeon Kim , Dong Il Han
发明人： Jong In Choi , Sang Yeon Kim , Dong Il Han
IPC分类号： G06F17/10
CPC分类号： G06T3/4023 , H03H17/0621 , H04N7/0135
摘要： A filter, in particular, a finite impulse response (FIR) filter having a variable data input and output rate is disclosed. The FIR filter includes a first-in first-out (FIFO) architectural buffer, an address generator for circularly generating respective addresses for FIFO of data items and providing the addresses to the buffer, a filter for performing filtering on data items having different rates, which are input from the buffer, and outputting one or more data, and a controller for controlling address generation of the address generator and controlling transfer paths of data items for filtering of the filter. It is possible to variably control the input and output rate of filtering data by the FIR filter.

9. 发明授权

US06700628B1 Device and method for controlling brightness of image signal 失效
标题翻译：用于控制图像信号亮度的装置和方法
公开(公告)号：US06700628B1
公开(公告)日：2004-03-02
申请号：US09567103
申请日：2000-05-08
申请人： Sang Yeon Kim
发明人： Sang Yeon Kim
IPC分类号： H04N514
CPC分类号： H04N5/20 , G06T5/009 , G06T5/40
摘要： A device and method for controlling a brightness of an image signal in a moving picture transmission/reception system is disclosed. The present invention includes a control point detecting unit for receiving an image, calculating a Cumulative Density Function from two most significant bits of the image, dividing an axis into a required number of portions, and detecting a required number of control points. The present invention also includes an image signal brightness controlling unit for calculating and dividing six least significant bits of the image and a signal from the control point detecting unit for controlling a next frame of the image.
摘要翻译：公开了一种用于控制运动图像发送/接收系统中的图像信号的亮度的装置和方法。本发明包括用于接收图像的控制点检测单元，从图像的两个最高有效位计算累积密度函数，将轴分成所需数量的部分，并且检测所需数量的控制点。本发明还包括图像信号亮度控制单元，用于计算和分割图像的六个最低有效位和来自控制点检测单元的信号，用于控制图像的下一帧。

10. 发明授权

US06204100B1 CMOS device and method for fabricating the same 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US06204100B1
公开(公告)日：2001-03-20
申请号：US09249314
申请日：1999-02-12
申请人： Sang Yeon Kim
发明人： Sang Yeon Kim
IPC分类号： H01L2100
CPC分类号： H01L27/1203 , H01L21/86
摘要： A CMOS device and a method for fabricating the same, is disclosed, the device including an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second epitaxial semiconductor layers formed on the first and second sapphire patterns, isolating structures formed at edges of the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacer structures formed at both sides of the first and second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacer structures, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film, first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impurity regions formed in the second semiconductor layer on both sides of the second gate electrodes. The CMOS device exhibits reduced latch-up and hot carrier characteristics, improved device reliability, reduced junction and parasitic capacitances, and improved device performance.
摘要翻译：公开了一种CMOS器件及其制造方法，该器件包括形成在衬底上的绝缘膜，以固定间隔形成在绝缘膜上的第一和第二蓝宝石图案，形成在第一和第二衬底上的第一和第二外延半导体层，第二蓝宝石图案，分别形成在第一和第二半导体层的边缘处的隔离结构，分别从第一和第二半导体层的表面形成为预定深度的第一和第二沟槽，形成在第一和第二半导体层的两侧的侧壁间隔结构沟槽，形成在侧壁间隔物结构之间的第一和第二半导体层中的每一个的表面上的栅极绝缘膜，分别形成在栅极绝缘膜上的第一和第二沟槽中的第一和第二栅极，形成的第一导电型杂质区在第一栅电极的两侧的第一半导体层中，第二栅极电极形成在第二栅电极两侧的第二半导体层中的导电型杂质区。 CMOS器件表现出减少的闭锁和热载流子特性，改进的器件可靠性，减少的结和寄生电容以及改进的器件性能。

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