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1. 发明授权

US07020832B2 Turbo decoder and its calculation methods having a state metric 失效
公开(公告)号：US07020832B2
公开(公告)日：2006-03-28
申请号：US10039005
申请日：2001-12-31
申请人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
发明人： In San Jeon , Hyuk Kim , Woo Seok Yang , Kyung Soo Kim , Whan Woo Kim , Han Jin Cho
IPC分类号： H03M13/03
CPC分类号： H03M13/3922 , H03M13/2957 , H03M13/6502 , H03M13/6505
摘要： The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

2. 发明申请

US20110154149A1 PARITY GENERATING APPARATUS AND MAP APPARATUS FOR TURBO DECODING 有权
标题翻译：用于涡轮解码的奇偶校验生成装置和地图装置
公开(公告)号：US20110154149A1
公开(公告)日：2011-06-23
申请号：US12972289
申请日：2010-12-17
申请人： In San Jeon , Hyuk Kim , Han Jin Cho
发明人： In San Jeon , Hyuk Kim , Han Jin Cho
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/6525 , H03M13/2957 , H03M13/3922 , H03M13/3927
摘要： An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.
摘要翻译：提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。

3. 发明授权

US08539325B2 Parity generating apparatus and map apparatus for turbo decoding 有权
标题翻译：用于turbo解码的奇偶校验生成装置和地图装置
公开(公告)号：US08539325B2
公开(公告)日：2013-09-17
申请号：US12972289
申请日：2010-12-17
申请人： In San Jeon , Hyuk Kim , Han Jin Cho
发明人： In San Jeon , Hyuk Kim , Han Jin Cho
IPC分类号： G06F11/00
CPC分类号： H03M13/6525 , H03M13/2957 , H03M13/3922 , H03M13/3927
摘要： An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.
摘要翻译：提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。

4. 发明申请

US20090147841A1 DISTRIBUTED VIDEO CODING APPARATUS AND METHOD CAPABLE OF CONTROLLING ENCODING RATE 失效
标题翻译：分布式视频编码设备和能够控制编码速率的方法
公开(公告)号：US20090147841A1
公开(公告)日：2009-06-11
申请号：US12142708
申请日：2008-06-19
申请人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

5. 发明授权

US08275032B2 Distributed video coding apparatus and method capable of controlling encoding rate 失效
标题翻译：能够控制编码率的分布式视频编码装置和方法
公开(公告)号：US08275032B2
公开(公告)日：2012-09-25
申请号：US12142708
申请日：2008-06-19
申请人： June Young Chang , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young Chang , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

6. 发明申请

US20100111438A1 ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE 审中-公开
标题翻译：基于边缘方向的各向异性扩散方法和装置
公开(公告)号：US20100111438A1
公开(公告)日：2010-05-06
申请号：US12612055
申请日：2009-11-04
申请人： June Young Chang , Han Jin Cho , Young Hwan Bae , Won Jong Kim , Mi Young Lee , Ju Yeob Kim , Guee Sang Lee , In San Jeon
发明人： June Young Chang , Han Jin Cho , Young Hwan Bae , Won Jong Kim , Mi Young Lee , Ju Yeob Kim , Guee Sang Lee , In San Jeon
IPC分类号： G06K9/40
CPC分类号： G06T5/002 , G06T5/20 , G06T2207/20012 , G06T2207/20192
摘要： An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.
摘要翻译：公开了一种基于边缘方向的各向异性扩散方法和装置。在各向异性扩散装置中，执行方向图案掩蔽以确定包括噪声的图像中的边缘的方向，并且通过方向图案掩模获得的值被卷积以计算图像的大小。如果边缘的计算幅度值大于阈值，则图像的边缘被保留，而如果所计算的边缘的幅度值不大于阈值，则噪声消除被加强，从而可以有效地产生噪声取消（或隐藏），同时保留表示图像特征的边缘，从而可以获得高质量的图像。

7. 发明授权

US08188801B2 Delay circuit for low power ring oscillator 失效
标题翻译：低功耗环形振荡器的延迟电路
公开(公告)号：US08188801B2
公开(公告)日：2012-05-29
申请号：US12878476
申请日：2010-09-09
申请人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
发明人： Myeung Su Kim , Han Jin Cho , Joon Hyung Lim , Kyung Hee Hong , Yong Il Kwon
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/012
摘要： Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.
摘要翻译：这里公开了一种用于低功率环形振荡器的延迟电路。延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

8. 发明授权

US07830959B2 Apparatus and method for performing intra prediction for image decoder 有权
标题翻译：用于对图像解码器进行帧内预测的装置和方法
公开(公告)号：US07830959B2
公开(公告)日：2010-11-09
申请号：US10876739
申请日：2004-06-28
申请人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
发明人： Seong Mo Park , Seung Chul Kim , Mi Young Lee , Han Jin Cho , Jong Dae Kim
IPC分类号： H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N19/436 , H04N19/105 , H04N19/186 , H04N19/423 , H04N19/44 , H04N19/593
摘要： Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16×16 luminance component and 4×4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.
摘要翻译：提供了一种用于对图像解码器进行帧内预测的装置和方法，其中通过使用与从外部设备输入的图像数据相邻的水平/垂直块，相对于16×16亮度分量并行执行帧内预测，图像数据的4×4亮度分量，然后相对于色度分量，从而最大化系统的效率，不仅减少了执行时间和硬件成本，而且提高了处理速度。

9. 发明申请

US20100150041A1 WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
标题翻译：具有自我感应功能的无线通信设备
公开(公告)号：US20100150041A1
公开(公告)日：2010-06-17
申请号：US12430313
申请日：2009-04-27
申请人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
发明人： Joon Hyung LIM , Tah Joon Park , Han Jin Cho , Myeung Su Kim , Sang Hoon Hwang , Kyung Hee Hong , Yong Il Kwon
IPC分类号： G08C17/00
CPC分类号： H04Q9/02 , H04Q2209/43 , H04Q2209/883
摘要： Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.
摘要翻译：公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

10. 发明授权

US07554355B2 Crossbar switch architecture for multi-processor SoC platform 有权
标题翻译：交叉开关架构为多处理器SoC平台
公开(公告)号：US07554355B2
公开(公告)日：2009-06-30
申请号：US11607515
申请日：2006-12-01
申请人： June Young Chang , Han Jin Cho
发明人： June Young Chang , Han Jin Cho
IPC分类号： H04L12/50 , H03K17/00
CPC分类号： H04L49/101 , H04L49/15 , H04L49/45
摘要： Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.
摘要翻译：提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易增加并具有简单的控制结构。交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与每行最后一列的多路复用器与该行的输入/输出线连接。

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