专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100111438A1 ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE 审中-公开
标题翻译：基于边缘方向的各向异性扩散方法和装置
公开(公告)号：US20100111438A1
公开(公告)日：2010-05-06
申请号：US12612055
申请日：2009-11-04
申请人： June Young Chang , Han Jin Cho , Young Hwan Bae , Won Jong Kim , Mi Young Lee , Ju Yeob Kim , Guee Sang Lee , In San Jeon
发明人： June Young Chang , Han Jin Cho , Young Hwan Bae , Won Jong Kim , Mi Young Lee , Ju Yeob Kim , Guee Sang Lee , In San Jeon
IPC分类号： G06K9/40
CPC分类号： G06T5/002 , G06T5/20 , G06T2207/20012 , G06T2207/20192
摘要： An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.
摘要翻译：公开了一种基于边缘方向的各向异性扩散方法和装置。在各向异性扩散装置中，执行方向图案掩蔽以确定包括噪声的图像中的边缘的方向，并且通过方向图案掩模获得的值被卷积以计算图像的大小。如果边缘的计算幅度值大于阈值，则图像的边缘被保留，而如果所计算的边缘的幅度值不大于阈值，则噪声消除被加强，从而可以有效地产生噪声取消（或隐藏），同时保留表示图像特征的边缘，从而可以获得高质量的图像。

2. 发明申请

US20090147841A1 DISTRIBUTED VIDEO CODING APPARATUS AND METHOD CAPABLE OF CONTROLLING ENCODING RATE 失效
标题翻译：分布式视频编码设备和能够控制编码速率的方法
公开(公告)号：US20090147841A1
公开(公告)日：2009-06-11
申请号：US12142708
申请日：2008-06-19
申请人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young CHANG , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

3. 发明授权

US08275032B2 Distributed video coding apparatus and method capable of controlling encoding rate 失效
标题翻译：能够控制编码率的分布式视频编码装置和方法
公开(公告)号：US08275032B2
公开(公告)日：2012-09-25
申请号：US12142708
申请日：2008-06-19
申请人： June Young Chang , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
发明人： June Young Chang , Han Jin Cho , Guee Sang Lee , Young Hwan Bae , In San Jeon , Won Jong Kim , Mi Young Lee , Ju Yeob Kim
IPC分类号： H04B1/66
CPC分类号： H04N19/137 , H04N19/115 , H04N19/61
摘要： There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.
摘要翻译：提供了一种能够控制编码率的分布式视频编码装置和方法，该装置包括：编码关键帧并输出编码关键帧的比特流的帧内编码器; 编码器速率控制（ERC）模块，通过使用运动复杂度和比特率之间的相关性，根据当前Wyner-Ziv（WZ）帧的运动复杂度来计算比特率; 以及通过在ERC模块处计算出的比特率编码当前WZ帧并输出编码的WZ比特流的turbo编码器。

4. 发明授权

US08890570B2 Switch block circuit in field programmable gate array 有权
标题翻译：现场可编程门阵列中的开关块电路
公开(公告)号：US08890570B2
公开(公告)日：2014-11-18
申请号：US13607637
申请日：2012-09-07
申请人： Han Jin Cho , Young Hwan Bae
发明人： Han Jin Cho , Young Hwan Bae
IPC分类号： H01L25/00 , H03K19/173 , G11C5/06
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/1776
摘要： A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.
摘要翻译：提供现场可编程门阵列中的开关块电路。开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

5. 发明授权

US07711787B2 On-chip network interfacing apparatus and method 有权
标题翻译：片上网络接口设备及方法
公开(公告)号：US07711787B2
公开(公告)日：2010-05-04
申请号：US11300731
申请日：2005-12-14
申请人： Jin Ho Han , Young Hwan Bae , Han Jin Cho , Jun Young Chang
发明人： Jin Ho Han , Young Hwan Bae , Han Jin Cho , Jun Young Chang
IPC分类号： G06F15/16
CPC分类号： H04L49/10 , H04L49/109 , H04L49/3009 , H04L49/3018 , H04L49/503
摘要： An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.
摘要翻译：提供了片上网络接口设备和方法。该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

6. 发明申请

US20130147516A1 SWITCH BLOCK CIRCUIT IN FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：现场可编程门阵列中的开关块电路
公开(公告)号：US20130147516A1
公开(公告)日：2013-06-13
申请号：US13607637
申请日：2012-09-07
申请人： Han Jin CHO , Young Hwan Bae
发明人： Han Jin CHO , Young Hwan Bae
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/1737 , H03K19/1776
摘要： A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.
摘要翻译：提供现场可编程门阵列中的开关块电路。开关块电路包括配置存储单元，其包括第一组存储器和第二组存储器，以及包括第一组开关晶体管和第二组开关晶体管的开关单元。开关块电路还包括用于根据操作模式相应地将第二组存储器与第二组开关晶体管连接的选择单元。切换块根据预期用途有效地可重新配置，并且在特定操作模式中未使用的配置存储器可以应用于其他目的。

7. 发明申请

US20110149984A1 CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME 审中-公开
标题翻译：使用FPGA和路由器系统中的配置存储器设备
公开(公告)号：US20110149984A1
公开(公告)日：2011-06-23
申请号：US12961752
申请日：2010-12-07
申请人： Han Jin CHO , Young Hwan Bae
发明人： Han Jin CHO , Young Hwan Bae
IPC分类号： H04L12/56 , G11C7/10
CPC分类号： H03K19/177
摘要： Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device.
摘要翻译：公开了一种配置存储装置和使用该配置存储装置的路由器系统。配置存储装置包括：选择单元，选择第一外部设备和存储单元中的一个并接收数据; 存储从所述选择单元接收的输入数据的寄存器; 存储单元，存储从寄存器接收的数据; 以及I / O单元，用于控制向寄存器和从第二外部设备发送和接收数据的I / O单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式