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1. 发明授权

US08104006B2 Method and apparatus for thermal analysis 有权
标题翻译：热分析方法和装置
公开(公告)号：US08104006B2
公开(公告)日：2012-01-24
申请号：US12024002
申请日：2008-01-31
申请人： Vinod Kariat , Igor Keller , Eddy Pramono
发明人： Vinod Kariat , Igor Keller , Eddy Pramono
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）布局的热分析的方法。在一些实施例中，该方法最初定义了几个功率耗散方程，其表示几个电路模块的功率耗散的温度依赖性。在一些实施例中，功耗方程表示功率耗散和温度之间的非线性关系。该方法基于指定的功率耗散方程定义热流方程。该方法然后解决了热流方程，以确定设计布局的温度分布。

2. 发明申请

US20090199140A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS 有权
标题翻译：用于热分析的方法和装置
公开(公告)号：US20090199140A1
公开(公告)日：2009-08-06
申请号：US12024002
申请日：2008-01-31
申请人： Vinod Kariat , Igor Keller , Eddy Pramono
发明人： Vinod Kariat , Igor Keller , Eddy Pramono
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express the temperature dependence of the power dissipation for several circuit modules. In some embodiments, the power dissipation equations express a non-linear relationship between power dissipation and temperature. The method defines a heat flow equation based on the specified power dissipation equations. The method then solves the heat flow equation to identify a temperature distribution for the design layout.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）布局的热分析的方法。在一些实施例中，该方法最初定义了几个功率耗散方程，其表示几个电路模块的功率耗散的温度依赖性。在一些实施例中，功耗方程表示功率耗散和温度之间的非线性关系。该方法基于指定的功率耗散方程定义热流方程。该方法然后解决了热流方程，以确定设计布局的温度分布。

3. 发明申请

US20120297357A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
公开(公告)号：US20120297357A1
公开(公告)日：2012-11-22
申请号：US13477006
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

4. 发明授权

US08104007B2 Method and apparatus for thermal analysis 有权
标题翻译：热分析方法和装置
公开(公告)号：US08104007B2
公开(公告)日：2012-01-24
申请号：US12144651
申请日：2008-06-24
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/16
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）设计布局的热分析的方法。该方法将IC设计布局分为一组元素，其中至少一个元素包含多个线。该方法计算一组元素的一组电导率值。该方法基于一组导电率值来识别IC设计布局的温度分布。在一些实施例中，这些元件中的每一个对应于IC设计布局的特定层的特定部分。每个元素包括几个节点。每个电导率值的值由入口值定义。每个入口值描述了元件的特定节点处的热流如何受到该元件的另一特定节点处的温度变化的影响。

5. 发明授权

US08566760B2 Method and apparatus for multi-die thermal analysis 有权
标题翻译：多模热分析的方法和装置
公开(公告)号：US08566760B2
公开(公告)日：2013-10-22
申请号：US13477005
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布在每个管芯上显示变化的温度。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

6. 发明申请

US20120304137A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
标题翻译：多模热分析方法与装置
公开(公告)号：US20120304137A1
公开(公告)日：2012-11-29
申请号：US13477005
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布在每个管芯上显示变化的温度。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

7. 发明申请

US20120210285A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) 有权
标题翻译：通过硅（TSV）热分析的方法和装置
公开(公告)号：US20120210285A1
公开(公告)日：2012-08-16
申请号：US13290047
申请日：2011-11-04
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

8. 发明申请

US20100023903A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
标题翻译：多模热分析方法与装置
公开(公告)号：US20100023903A1
公开(公告)日：2010-01-28
申请号：US12180490
申请日：2008-07-25
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F9/45
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布显示出每个管芯的温度变化。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

9. 发明申请

US20090319965A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) 有权
标题翻译：通过硅（TSV）热分析的方法和装置
公开(公告)号：US20090319965A1
公开(公告)日：2009-12-24
申请号：US12416793
申请日：2009-04-01
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

10. 发明授权

US08543952B2 Method and apparatus for thermal analysis of through-silicon via (TSV) 有权
标题翻译：通硅（TSV）热分析方法及装置
公开(公告)号：US08543952B2
公开(公告)日：2013-09-24
申请号：US13290047
申请日：2011-11-04
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

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