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1. 发明申请

WO2020226979A2 MULTI-ENTITY RESOURCE, SECURITY, AND SERVICE MANAGEMENT IN EDGE COMPUTING DEPLOYMENTS 审中-公开
公开(公告)号：WO2020226979A2
公开(公告)日：2020-11-12
申请号：PCT/US2020/030554
申请日：2020-04-29
申请人： INTEL CORPORATION
发明人： GUIM BERNAT, Francesc , ASTILLEROS, Ignacio , BALLE, Susanne M. , BARTFAI-WALCOTT, Katalin , BROWNE, John J. , CHEN, Li , COOPER, Trevor , USTODIO, Evan , DOSHI, Kshitij Arun , FILIPPOU, Miltiadis , GANESH, Brinda , HERDRICH, Andrew J. , IYER, Ravishankar R. , JAIN, Nilesh , KUMAR, Karthik , KUTCH, Patrick G. , MACIOCCO, Christian , PARKER, Valerie J. , PASTOR BENEYTO, Felipe , POORNACHANDRAN, Rajesh , POWER, Damien , PRABHAKARAN, Suraj , SCHOOLER, Eve M. , SMITH, Ned M. , SOOD, Kapil , TAHHAN, Maryam , VERRALL, Timothy , VISWANATHAN, Tarun , VON BOKERN, Vincent , WALSH, Eoin , WILLHALM, Thomas , SETHURAMAN, Ramanathan , PATEL, Rashmin , VERPLANKE, Edwin , SHAH, Rahul R.
IPC分类号： H04L29/08 , H04L12/24 , H04L29/06 , H04W76/15 , H04W88/18 , G06F1/206 , G06F11/3006 , G06F2209/5021 , G06F9/4881 , G06F9/505 , G06F9/5061 , G06F9/5072 , G06F9/5094 , G06F9/542 , H04L41/0843 , H04L41/0869 , H04L41/5054 , H04L47/781 , H04L49/70 , H04L9/0637 , H04L9/3213 , H04L9/3247
摘要： Various aspects of methods, systems, and use cases for multi-entity (e.g., multi-tenant) edge computing deployments are disclosed. Among other examples, various configurations and features enable the management of resources (e.g., controlling and orchestrating hardware, acceleration, network, processing resource usage), security (e.g., secure execution and communication, isolation, conflicts), and service management (e.g., orchestration, connectivity, workload coordination), in edge computing deployments, such as by a plurality of edge nodes of an edge computing environment configured for executing workloads from among multiple tenants.

2. 发明申请

WO2017049590A1 SYSTEMS AND METHODS FOR INPUT/OUTPUT COMPUTING RESOURCE CONTROL 审中-公开
标题翻译：用于输入/输出计算资源控制的系统和方法
公开(公告)号：WO2017049590A1
公开(公告)日：2017-03-30
申请号：PCT/CN2015/090737
申请日：2015-09-25
申请人： INTEL CORPORATION , LIANG, Cunming , VERPLANKE, Edwin , COHEN, David E. , ZHOU, Danny
发明人： LIANG, Cunming , VERPLANKE, Edwin , COHEN, David E. , ZHOU, Danny
IPC分类号： G06F12/02
CPC分类号： G06F21/85
摘要： Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, ahost device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container ofthe host device. The Tag ID may identify a queue pair ofa hardware device ofthe host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.
摘要翻译：这里公开了用于隔离输入/输出计算资源的系统和方法。在一些实施例中，主机设备可以包括与处理器耦合的处理器和逻辑，以识别用于主机设备的进程或容器的标签标识符（Tag ID）。标签ID可以标识主机设备的硬件设备的队列对，用于从处理器到硬件设备的出站事务，由进程或容器进行。逻辑可以进一步将标签ID映射到与来自硬件设备的入站事务相关联的进程地址空间标识符（PASID）到使用所识别的队列对的处理器。进程或容器可以使用PASID通过识别的队列对进行出站事务。可以公开和/或要求保护其他实施例。

3. 发明申请

WO2023049584A1 NETWORK LAYER 7 OFFLOAD TO INFRASTRUCTURE PROCESSING UNIT FOR SERVICE MESH 审中-公开
公开(公告)号：WO2023049584A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075335
申请日：2022-08-23
申请人： INTEL CORPORATION
发明人： GANGULI, Mrittika , JAIN, Anjali , LAL, Reshma , VERPLANKE, Edwin , AUTEE, Priya , CHANG, Chih-Jen , LAYEK, Abhirupa , JAIN, Nupur
IPC分类号： G06F9/50 , G06F9/54 , H04L67/289 , H04L69/321
摘要： Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

4. 发明申请

WO2017052935A1 OUT-OF-BAND PLATFORM TUNING AND CONFIGURATION 审中-公开
标题翻译：带外平台调谐和配置
公开(公告)号：WO2017052935A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048478
申请日：2016-08-24
申请人： INTEL CORPORATION
发明人： HERDRICH, Andrew J. , CONNOR, Patrick L. , KUMAR, Dinesh , MIN, Alexander W. , DAHLE, Daniel J. , SOOD, Kapil , SHAW, Jeffrey B. , VERPLANKE, Edwin , DUBAL, Scott P. , HEARN, James R.
IPC分类号： H04L12/24 , H04L12/931
CPC分类号： H04Q9/02 , H04L41/5009 , H04L41/5019 , H04L43/08 , H04L43/10
摘要： Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.
摘要翻译：本文描述了用于带外平台调整和配置的设备和技术。设备可以包括遥测收集系统的遥测接口和网络适配器硬件的网络接口。该设备可以从遥测收集系统接收平台遥测指标，并通过网络接口接收网络适配器硅硬件统计信息，收集采集的统计信息。设备可以使用所收集的统计信息来应用启发式算法，以确定通过通信地耦合到该设备的多个软件系统的操作产生的处理核心工作负载。响应于基于处理核心工作负载来检测至少一个处理核心上的过载状态，该设备可以提供重新配置消息以指示至少一个软件系统将操作切换到不同的处理核心。还描述了其它实施例。

5. 发明申请

WO2022139920A1 RESOURCE MANAGER ACCESS CONTROL 审中-公开
公开(公告)号：WO2022139920A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/051793
申请日：2021-09-23
申请人： INTEL CORPORATION
发明人： HERDRICH, Andrew J. , AUTEE, Priya , SANKARAN, Rajesh M. , NEIGER, Gilbert , OEHRLEIN, Scott , PRINKE, Michael , IYER, Ravishankar , VERPLANKE, Edwin
IPC分类号： G06F9/50 , G06F9/30 , G06F9/455
摘要： Examples provide a system that includes one or more processors, that when operational, are to: based on content in a request being within a permitted range for a virtualized execution environment, transfer the request from the virtualized execution environment to reserve one or more device resources independent from causing a virtual machine exit to request to reserve one or more device resources. In some examples, the transfer comprises a write to a register. In some examples, processor-executed microcode is to determine whether content in the request is within a permitted range for the virtualized execution environment.

6. 发明申请

WO2017123390A1 INTERRUPTS BETWEEN VIRTUAL MACHINES 审中-公开
标题翻译：虚拟机之间的中断
公开(公告)号：WO2017123390A1
公开(公告)日：2017-07-20
申请号：PCT/US2016/067849
申请日：2016-12-20
申请人： INTEL CORPORATION
发明人： TSAI, Jr-Shian , SAHITA, Ravi, L. , ERGIN, Mesut, A. , SANKARAN, Rajesh, M. , NEIGER, Gilbert , NAKAJIMA, Jun , VERPLANKE, Edwin , HUNTLEY, Barry, E. , TAI, Tsung-Yuan, C.
IPC分类号： G06F9/32 , G06F9/30
CPC分类号： G06F13/24 , G06F9/45558 , G06F2009/45575 , G06F2009/45579
摘要： Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.
摘要翻译：公开了虚拟机之间的本发明中断的实施例。在一个实施例中，处理器包括指令单元和执行单元，二者至少部分地以处理器的硬件实现。指令单元将接收向目标虚拟机发送中断的指令。执行单元将在不退出发送虚拟机的情况下在发送虚拟机上执行该指令。执行指令包括使用指令指定的句柄来查找发布的中断描述符。

7. 发明申请

WO2017119980A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
标题翻译：使用硬件排队设备的多核通信加速
公开(公告)号：WO2017119980A1
公开(公告)日：2017-07-13
申请号：PCT/US2016/065170
申请日：2016-12-06
申请人： INTEL CORPORATION
发明人： WANG, Ren , WANG, Yipeng , HERDRICH, Andrew J. , TSAI, Jr-Shian , TAI, Tsung-Yuan C. , MCDONNELL, Niall D. , WILKINSON, Hugh , BURRES, Bradley A. , RICHARDSON, Bruce , VENKATESAN, Namakkal N. , BERNSTEIN, Debra , VERPLANKE, Edwin , VAN DOREN, Stephen R. , YAN, An , CUNNINGHAM, Andrew , SONNIER, David , EADS, Gage , CLEE, James T. , WHITESELL, Jamison D. , PIROG, Jerry , KENNY, Jonathan , HASTING, Joseph R. , VANGATI, Narender , MILLER, Stephen , MA, Te K. , BURROUGHS, William
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F13/37 , G06F12/0811 , G06F13/1642 , G06F13/1673 , G06F2212/283
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.
摘要翻译：实现硬件队列管理设备的装置和方法，用于通过从CPU核卸载请求管理和数据一致性任务来减少核心间数据传输开销。该设备包括多核处理器，共享的L3或最后一级高速缓存（“LLC”）以及用于接收，存储和处理核心间数据传输请求的硬件队列管理设备。硬件队列管理设备还包括资源管理系统，用于控制核心可以提交请求以降低核心停顿和丢弃的请求的速率。此外，还引入了软件指令来优化内核与队列管理设备之间的通信。

8. 发明申请

WO2017112256A1 TECHNOLOGIES FOR ENFORCING NETWORK ACCESS CONTROL OF VIRTUAL MACHINES 审中-公开
标题翻译：用于实现虚拟机网络访问控制的技术
公开(公告)号：WO2017112256A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063334
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： PALERMO, Stephen T. , TADEPALLI, Hari K. , PATEL, Rashmin N. , HERDRICH, Andrew J. , VERPLANKE, Edwin
IPC分类号： G06F9/455
CPC分类号： H04L63/04 , G06F21/53 , G06F2221/2141 , H04L41/0806 , H04L41/0893 , H04L43/0847 , H04L63/102
摘要： Technologies for enforcing virtual machine network access control include a network computing device that includes a plurality of virtual machines. The network computing device is configured to receive an access request from a virtual function assigned to a requesting virtual machine of the network computing device. The network computing device is additionally configured to determine a first privilege level assigned to the requesting machine and a second privilege level assigned to the destination virtual machine, and determine whether the requesting virtual machine is authorized to access the destination virtual machine based on a comparison of the first and second privilege levels. Upon determining the requesting virtual machine is authorized to access the destination virtual machine, the network computing device is additionally configured to allow the requesting virtual machine access to the destination virtual machine. Other embodiments are described herein.
摘要翻译：用于实施虚拟机网络访问控制的技术包括包括多个虚拟机的网络计算设备。网络计算设备被配置为从分配给网络计算设备的请求虚拟机的虚拟功能接收访问请求。网络计算设备另外被配置为确定分配给请求机器的第一特权级别和分配给目的地虚拟机的第二特权级别，并且基于以下内容的比较来确定请求虚拟机是否被授权访问目的地虚拟机第一和第二特权级别。在确定请求虚拟机被授权访问目的地虚拟机之后，网络计算设备另外被配置为允许请求虚拟机访问目的地虚拟机。这里描述了其他实施例。

10. 发明公开

EP4273704A2 TECHNIQUES TO SUPPORT A HOLISTIC VIEW OF CACHE CLASS OF SERVICE FOR A PROCESSOR CACHE 审中-实审
公开(公告)号：EP4273704A2
公开(公告)日：2023-11-08
申请号：EP23198376.8
申请日：2018-06-29
申请人： INTEL Corporation
发明人： BHANDARU, Malini K. , GASPARAKIS, Iosif , RANGANATH, Sunku , QIAO, Liyong , ZANG, Rui , ILANGOVAN, Dakshina , FENG, Shaohe , VERPLANKE, Edwin , AUTEE, Priya , YANG, Lin A.
IPC分类号： G06F12/0864
摘要： Examples include techniques to support a holistic view of cache class of service (CLOS). Examples include allocating processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.

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