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    • 8. 发明申请
    • PROCESSORS, METHODS, AND SYSTEMS TO ALLOCATE LOAD AND STORE BUFFERS BASED ON INSTRUCTION TYPE
    • 根据指令类型分配装载和存储缓冲区的处理器,方法和系统
    • WO2017172256A1
    • 2017-10-05
    • PCT/US2017/020585
    • 2017-03-03
    • INTEL CORPORATION
    • HERDRICH, Andrew J.WANG, YipengWANG, RenTAI, Tsung-Yuan C.TSAI, Jr-Shian
    • G06F13/16G06F9/50
    • G06F9/30043G06F9/30047G06F9/3824G06F9/3836G06F12/0804G06F12/0862G06F2212/6028
    • A processor of an aspect includes a decode unit to decode memory access instructions of a first type and to output corresponding memory access operations, and to decode memory access instructions of a second type and to output corresponding memory access operations. The processor also includes a load store queue coupled with the decode unit. The load store queue includes a load buffer that is to have a plurality of load buffer entries, and a store buffer that is to have a plurality of store buffer entries. The load store queue also includes a buffer entry allocation controller coupled with the load buffer and coupled with the store buffer. The buffer entry allocation controller is to allocate load and store buffer entries based at least in part on whether memory access operations correspond to memory access instructions of the first type or of the second type. Other processors, methods, and systems, are also disclosed.
    • 一个方面的处理器包括解码单元,用于解码第一类型的存储器访问指令并输出相应的存储器访问操作,并且解码第二类型的存储器访问指令并输出相应的存储器访问 操作。 处理器还包括与解码单元耦合的加载存储队列。 加载存储器队列包括具有多个加载缓冲器条目的加载缓冲器以及具有多个存储缓冲器条目的存储缓冲器。 加载存储队列还包括与加载缓冲器耦合并与存储缓冲器耦合的缓冲器入口分配控制器。 缓冲器入口分配控制器至少部分地基于存储器访问操作是对应于第一类型还是第二类型的存储器访问指令来分配加载和存储缓冲器条目。 其他处理器,方法和系统也被公开。