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1. 发明申请

WO2022271246A1 NETWORK INTERFACE DEVICE MANAGEMENT OF SERVICE EXECUTION FAILOVER 审中-公开
公开(公告)号：WO2022271246A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/022028
申请日：2022-03-25
申请人： INTEL CORPORATION
发明人： GUIM BERNAT, Francesc , KUMAR, Karthik , BACHMUTSKY, Alexander , KUTCH, Patrick G. , CARRANZA, Marcos E.
IPC分类号： G06F11/20 , G06F9/48 , G06F11/0709 , G06F11/0757 , G06F11/2007 , G06F11/2028 , G06F11/2038 , G06F11/2048 , G06F11/3006 , G06F11/3058 , G06F11/3419 , G06F11/3447 , G06F11/3476 , G06F2201/85 , G06F2201/875 , G06F9/4856 , G06F9/5072
摘要： Examples described herein relate to a network interface device that comprises circuitry, when operational, to select a platform to execute a function and based on load of the platform, selectively cause the function to execute on one or more other platforms to attempt to achieve or finish before the time-to-completion. In some examples, the circuitry is to detect progress of function execution to determine whether completion of execution of the function is predicted to not finish within the time-to-completion and cause the function to execute on one or more other platforms based on completion of execution of the function predicted to not finish within the time-to-completion.

2. 发明申请

WO2021225637A1 NETWORK AND EDGE ACCELERATION TILE (NEXT) ARCHITECTURE 审中-公开
公开(公告)号：WO2021225637A1
公开(公告)日：2021-11-11
申请号：PCT/US2020/067073
申请日：2020-12-26
申请人： INTEL CORPORATION
发明人： KUTCH, Patrick G. , CHILIKIN, Andrey , MCDONNELL, Niall D. , KEATING, Brian A. , LAKKAKULA, Naveen , GANGA, Ilango S. , KRISHNA IYER, Venkidesh , FLEMING, Patrick , MOSUR, Lokpraveen
IPC分类号： H04L12/935 , H04L12/879 , H04L12/861 , H04L12/867 , H04L12/937 , H04L12/851 , H04L29/08 , G06F9/50 , H04L29/06
摘要： Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

3. 发明申请

WO2020226979A2 MULTI-ENTITY RESOURCE, SECURITY, AND SERVICE MANAGEMENT IN EDGE COMPUTING DEPLOYMENTS 审中-公开
公开(公告)号：WO2020226979A2
公开(公告)日：2020-11-12
申请号：PCT/US2020/030554
申请日：2020-04-29
申请人： INTEL CORPORATION
发明人： GUIM BERNAT, Francesc , ASTILLEROS, Ignacio , BALLE, Susanne M. , BARTFAI-WALCOTT, Katalin , BROWNE, John J. , CHEN, Li , COOPER, Trevor , USTODIO, Evan , DOSHI, Kshitij Arun , FILIPPOU, Miltiadis , GANESH, Brinda , HERDRICH, Andrew J. , IYER, Ravishankar R. , JAIN, Nilesh , KUMAR, Karthik , KUTCH, Patrick G. , MACIOCCO, Christian , PARKER, Valerie J. , PASTOR BENEYTO, Felipe , POORNACHANDRAN, Rajesh , POWER, Damien , PRABHAKARAN, Suraj , SCHOOLER, Eve M. , SMITH, Ned M. , SOOD, Kapil , TAHHAN, Maryam , VERRALL, Timothy , VISWANATHAN, Tarun , VON BOKERN, Vincent , WALSH, Eoin , WILLHALM, Thomas , SETHURAMAN, Ramanathan , PATEL, Rashmin , VERPLANKE, Edwin , SHAH, Rahul R.
IPC分类号： H04L29/08 , H04L12/24 , H04L29/06 , H04W76/15 , H04W88/18 , G06F1/206 , G06F11/3006 , G06F2209/5021 , G06F9/4881 , G06F9/505 , G06F9/5061 , G06F9/5072 , G06F9/5094 , G06F9/542 , H04L41/0843 , H04L41/0869 , H04L41/5054 , H04L47/781 , H04L49/70 , H04L9/0637 , H04L9/3213 , H04L9/3247
摘要： Various aspects of methods, systems, and use cases for multi-entity (e.g., multi-tenant) edge computing deployments are disclosed. Among other examples, various configurations and features enable the management of resources (e.g., controlling and orchestrating hardware, acceleration, network, processing resource usage), security (e.g., secure execution and communication, isolation, conflicts), and service management (e.g., orchestration, connectivity, workload coordination), in edge computing deployments, such as by a plurality of edge nodes of an edge computing environment configured for executing workloads from among multiple tenants.

4. 发明申请

WO2012166751A2 CIRCUITRY TO MAINTAIN CORRELATION BETWEEN SETS OF ADDRESSES 审中-公开
标题翻译：电路维护地址之间的相关性
公开(公告)号：WO2012166751A2
公开(公告)日：2012-12-06
申请号：PCT/US2012/039903
申请日：2012-05-29
申请人： INTEL CORPORATION , KUTCH, Patrick G.
发明人： KUTCH, Patrick G.
IPC分类号： H04L29/08 , H04L29/12
CPC分类号： H04L61/103
摘要： An embodiment may include circuitry in a controller that may be included in a host that has at least one processor. The circuitry may maintain a correlation between a set of network addresses and a set of medium access control (MAC) addresses. The correlation may be generated, at least in part, by at least one process to be executed, at least in part, by the at least one processor. The circuitry may determine, based at least in part upon the set of network addresses, whether to generate at least one response to at least one request. If the circuitry determines to generate the at least one response, the circuitry may generate the at least one response based at least in part upon the correlation and at least one network address associated with the at least one request. Many alternatives, variations, and modifications are possible.
摘要翻译：实施例可以包括可以包括在具有至少一个处理器的主机中的控制器中的电路。电路可以保持一组网络地址和一组介质访问控制（MAC）地址之间的相关性。该相关可以至少部分地由至少一个处理器至少部分地由至少一个处理器执行的至少一个处理产生。该电路可至少部分地基于该组网络地址来确定是否对至少一个请求生成至少一个响应。如果电路确定产生至少一个响应，则电路可以至少部分地基于相关性和与至少一个请求相关联的至少一个网络地址来生成至少一个响应。许多替代方案，变化和修改是可能的。

5. 发明申请

WO2021225628A1 MEMORY ALLOCATION FOR DISTRIBUTED PROCESSING DEVICES 审中-公开
公开(公告)号：WO2021225628A1
公开(公告)日：2021-11-11
申请号：PCT/US2020/065076
申请日：2020-12-15
申请人： INTEL CORPORATION
发明人： KUTCH, Patrick G. , CHILIKIN, Andrey
IPC分类号： G06F13/16 , G06F13/30
摘要： Examples described herein relate to an offload processor to receive data for transmission using a network interface or received in a packet by a network interface. In some examples, the offload processor can include a packet storage controller to determine whether to store data in a buffer of the offload processing device or a system memory after processing by the offload processing device. In some examples, determine whether to store data in a buffer of the offload processor or a system memory is based on one or more of: available buffer space, latency limit associated with the data, priority associated with the data, or available bandwidth through an interface between the buffer and the system memory. In some examples, the offload processor is to receive a descriptor and specify a storage location of data in the descriptor, wherein the storage location is within the buffer or the system memory.

6. 发明申请

WO2013016433A1 FACILITATING COMPATIBLE INTERACTION, AT LEAST IN PART 审中-公开
标题翻译：促进兼容性相互作用，至少部分
公开(公告)号：WO2013016433A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/048156
申请日：2012-07-25
申请人： INTEL CORPORATION , KUTCH, Patrick G.
发明人： KUTCH, Patrick G.
IPC分类号： G06F1/00 , G06F9/44
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： An embodiment may include circuitry to determine compatibility, at least in part, of a device with at least one process intended to interact with, at least in part, the device. Such compatibility may be determined by the circuitry based at least in part upon at least one feature set of the device. If the device is incompatible, at least in part, with the at least one process, the circuitry may identify, at least in part, the device in manner that facilitates compatible interaction, at least in part, between the at least one process and at least one portion of the at least one feature set. Many alternatives, variations, and modifications are possible.
摘要翻译：一个实施例可以包括至少部分地确定具有至少一个进程的装置的兼容性的电路，该至少一个进程旨在至少部分地与装置进行交互。这种兼容性可以由至少部分地基于设备的至少一个特征集的电路来确定。如果设备至少部分地与至少一个过程不兼容，则电路可以至少部分地以便于至少部分地在至少一个进程和在至少一个进程之间进行兼容交互的方式来识别设备所述至少一个特征集的至少一部分。许多替代方案，变化和修改是可能的。

7. 发明公开

EP4104419A1 HARDWARE-ASSISTED TRACING SCHEMES FOR DISTRIBUTED AND SCALE-OUT APPLICATIONS 审中-实审
公开(公告)号：EP4104419A1
公开(公告)日：2022-12-21
申请号：EP20918341.7
申请日：2020-11-17
申请人： INTEL Corporation
发明人： GUIM BERNAT, Francesc , KUTCH, Patrick G. , COOPER, Trevor , VERRALL, Timothy , KUMAR, Karthik
IPC分类号： H04L29/08 , H04L12/24

9. 发明授权

EP2991306B1 TECHNOLOGIES FOR ALIGNING NETWORK FLOWS TO PROCESSING RESOURCES 有权
标题翻译：用于调整网络流量以处理资源的技术
公开(公告)号：EP2991306B1
公开(公告)日：2017-08-23
申请号：EP15176666.4
申请日：2015-07-14
申请人： Intel Corporation
发明人： GASPARAKIS, Iosif , JOHNSON, Brian P. , KUTCH, Patrick G.
IPC分类号： H04L29/08 , G06F9/48 , H04L12/801 , H04L12/24
CPC分类号： H04L47/33 , G06F9/48 , H04L41/044 , H04L47/35 , H04L67/1002 , H04L67/327 , H04L69/321 , H04L69/329

10. 发明公开

EP2716013A2 CIRCUITRY TO MAINTAIN CORRELATION BETWEEN SETS OF ADDRESSES 审中-公开
标题翻译：电路是否相关地址集之间CARE
公开(公告)号：EP2716013A2
公开(公告)日：2014-04-09
申请号：EP12793859.5
申请日：2012-05-29
申请人： Intel Corporation
发明人： KUTCH, Patrick G.
IPC分类号： H04L29/08 , H04L29/12
CPC分类号： H04L61/103
摘要： An embodiment may include circuitry in a controller that may be included in a host that has at least one processor. The circuitry may maintain a correlation between a set of network addresses and a set of medium access control (MAC) addresses. The correlation may be generated, at least in part, by at least one process to be executed, at least in part, by the at least one processor. The circuitry may determine, based at least in part upon the set of network addresses, whether to generate at least one response to at least one request. If the circuitry determines to generate the at least one response, the circuitry may generate the at least one response based at least in part upon the correlation and at least one network address associated with the at least one request. Many alternatives, variations, and modifications are possible.

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