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1. 发明申请

WO2007109921A1 METHODS AND APPARATUS TO IMPLEMENT ANNOTATION BASED THUNKING 审中-公开
标题翻译：方法和设备实现基于假设的假设
公开(公告)号：WO2007109921A1
公开(公告)日：2007-10-04
申请号：PCT/CN2006/000529
申请日：2006-03-28
申请人： INTEL CORPORATION , HUANG, Bo , LIU, Jiangning , GAO, Lei
发明人： HUANG, Bo , LIU, Jiangning , GAO, Lei
IPC分类号： G06F9/00
CPC分类号： G06F9/455
摘要： Methods and apparatus to implement annotation based thunking are disclosed. An example method comprises locating a parameter of a function, the parameter to be passed as a pointer if a size of the parameter is greater than a threshold and to be passed as data if the size of the parameter is not greater than the threshold, and adding an annotation record for the parameter to a byte code image file containing byte code for the function.
摘要翻译：披露了实施基于注解的拆分的方法和装置。一种示例性方法包括：如果参数的大小大于阈值，则定位要被传递的参数作为指针的参数，并且如果参数的大小不大于阈值则作为数据传递;以及将参数的注释记录添加到包含该函数的字节码的字节码图像文件中。

2. 发明申请

WO2007016808A1 A COMPILING AND TRANSLATING METHOD AND APPARATUS 审中-公开
标题翻译：编译和翻译方法和装置
公开(公告)号：WO2007016808A1
公开(公告)日：2007-02-15
申请号：PCT/CN2005/001204
申请日：2005-08-05
申请人： INTEL CORPORATION , LI, Jianhui , WANG, Yun , HUANG, Bo , LE, Yongnian , LIU, Jiangning , YE, Jinyun
发明人： LI, Jianhui , WANG, Yun , HUANG, Bo , LE, Yongnian , LIU, Jiangning , YE, Jinyun
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Methods and apparatus are described to compile and translate source code. In some embodiments, source code is compiled into source binary code for a source platform; an annotation section associated with the source binary code is generated, wherein the annotation section comprises an annotation for a scope, the scope comprising at least one dock of the source binary code having at least one attribute to aid a translator optimization. If the scope comprises a plurality of blocks, the blocks have consecutive addresses with each other and have the at least one attribute in common. In the embodiments, the source binary code is further translated into target binary code for a target platform by utilizing the annotation section.
摘要翻译：描述了编译和翻译源代码的方法和设备。在一些实施例中，源代码被编译为源平台的源二进制代码; 生成与源二进制代码相关联的注释部分，其中注释部分包括范围的注释，所述范围包括具有至少一个属性的源二进制代码的至少一个基座，以帮助翻译器优化。如果范围包括多个块，则这些块具有彼此的连续地址并具有共同的至少一个属性。在实施例中，源二进制码通过利用注释部分进一步转换为目标平台的目标二进制代码。

3. 发明申请

WO2007076622A1 EVALUATION AND SELECTION OF PROGRAMMING CODE 审中-公开
标题翻译：评估和选择编程代码
公开(公告)号：WO2007076622A1
公开(公告)日：2007-07-12
申请号：PCT/CN2005/002384
申请日：2005-12-30
申请人： INTEL CORPORATION , HUANG, Bo , SUN, Yuanhao , GAO, Lei , LI, Jianhui
发明人： HUANG, Bo , SUN, Yuanhao , GAO, Lei , LI, Jianhui
IPC分类号： G06F7/32
CPC分类号： G06F8/443
摘要： A system for evaluating and selecting programming code is described. A first evaluator measures a first characteristic of a number of input binaries. The evaluator computes a number of first figures of merit for the input binaries, respectively. A binary selector compares the first figures of merit, and selects one of the input binaries as having the highest or lowest overall figure of merit. Other embodiments are also described and claimed.
摘要翻译：描述用于评估和选择节目代码的系统。第一个评估者测量多个输入二进制文件的第一个特征。评估者分别计算输入二进制文件的第一个品质因数。二进制选择器比较第一个品质因数，并选择其中一个输入二进制文件具有最高或最低总体品质因数。还描述和要求保护其他实施例。

4. 发明申请

WO2015085542A1 VOICE PERSONALIZATION FOR MACHINE READING 审中-公开
标题翻译：机器阅读的语音个性化
公开(公告)号：WO2015085542A1
公开(公告)日：2015-06-18
申请号：PCT/CN2013/089236
申请日：2013-12-12
申请人： INTEL CORPORATION , LI, Honggang , ZHU, Yuan , HUANG, Bo , YANG, Liu
发明人： LI, Honggang , ZHU, Yuan , HUANG, Bo , YANG, Liu
IPC分类号： G10L13/02 , G06F3/16
CPC分类号： G10L13/033 , G06F3/165 , G09B21/006 , G10L13/10 , H04L63/10
摘要： Systems and techniques of voice personalization for machine reading are described herein. A message with textual content maybe received. A sender of the message maybe identified. A voice model that corresponds to the sender maybe identified. An audio representation of the textual content maybe rendered using the voice model.
摘要翻译：本文描述了用于机器读取的语音个性化的系统和技术。可能收到带有文本内容的消息。消息的发送者可能被识别。可以识别与发送者对应的语音模型。可以使用语音模型来呈现文本内容的音频表示。

5. 发明申请

WO2005116837A1 AUTOMATIC CACHING GENERATION IN NETWORK APPLICATIONS 审中-公开
标题翻译：网络应用中的自动高速缓存生成
公开(公告)号：WO2005116837A1
公开(公告)日：2005-12-08
申请号：PCT/CN2004/000538
申请日：2004-05-26
申请人： INTEL CORPORATION , DAI, Jinquan , HARRISON, Luddy , LI, Long , HUANG, Bo
发明人： DAI, Jinquan , HARRISON, Luddy , LI, Long , HUANG, Bo
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F8/4442 , G06F12/0893
摘要： Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses is identified, where the external memory accesses have a substantially identical base address. One or more directives and/or instructions are inserted into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor, and to modify at least one of the external memory access to access at least one of the CAM and LM of the processor without having to perform the respective external memory access. Other methods and apparatuses are also described.
摘要翻译：本文描述了网络应用中自动软件控制的缓存世代。在一个实施例中，识别表示执行一个或多个外部存储器访问的多个线程的多个指令的候选者，其中外部存储器访问具有基本上相同的基地址。将一个或多个指令和/或指令插入与所识别的候选对应的指令流中，以维持处理器的内容可寻址存储器（CAM）和本地存储器（LM）中的至少一个的内容，并修改至少一个的外部存储器访问以访问处理器的CAM和LM中的至少一个，而不必执行相应的外部存储器访问。还描述了其它方法和装置。

6. 发明申请

WO2005050445A2 AN APPARATUS AND METHOD FOR AN AUTOMATIC THREAD-PARTITION COMPILER 审中-公开
标题翻译：一种用于自动线程分割编译器的装置和方法
公开(公告)号：WO2005050445A2
公开(公告)日：2005-06-02
申请号：PCT/US2004/037161
申请日：2004-11-05
申请人： INTEL CORPORATION , LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
发明人： LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F9/4843
摘要： In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as a respective threads of multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，描述了一种用于自动线程分区编译器的方法和装置。在一个实施例中，该方法包括将顺序应用程序转换成多个应用程序线程。一旦分区，多个应用程序线程作为多线程体系结构的相应线程同时执行。因此，并行多线程体系结构的性能改进是通过隐藏存储器访问延迟或通过将存储器访问与计算或其他存储器访问重叠来实现的。描述并要求保护其他实施例。

7. 发明申请

WO2005050444A3 AN APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELIZING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION 审中-公开
公开(公告)号：WO2005050444A3
公开(公告)日：2005-06-02
申请号：PCT/US2004/037160
申请日：2004-11-05
申请人： INTEL CORPORATION , DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
发明人： DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
IPC分类号： G06F9/45
摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

8. 发明申请

WO2008077266A1 ENTERPRISE KNOWLEDGE MANAGEMENT AND SHARING METHOD AND APPARATUS 审中-公开
标题翻译：企业知识管理与共享方法与设备
公开(公告)号：WO2008077266A1
公开(公告)日：2008-07-03
申请号：PCT/CN2006/003532
申请日：2006-12-22
申请人： INTEL CORPORATION , DING, Jonathan, Junyong , HUANG, Bo , ZHANG, Wenjie
发明人： DING, Jonathan, Junyong , HUANG, Bo , ZHANG, Wenjie
IPC分类号： G06F17/30
CPC分类号： G06F17/3089 , G06Q10/00 , G06Q10/103
摘要： An enterprise knowledge management and sharing system having a plurality of services to facilitate members of an enterprise to create, capture, organize, refine, promote and/or publish knowledge of the enterprise is disclosed and described herein.
摘要翻译：本文公开并描述了具有多个服务的企业知识管理和共享系统，以便于企业成员创建，捕获，组织，改进，促进和/或发布企业的知识。

9. 发明申请

WO2005098619A1 A METHOD AND SYSTEM FOR ASSIGNING REGISTER CLASS THROUGH EFFICIENT DATAFLOW ANALYSIS 审中-公开
标题翻译：一种通过有效数据流分析来注册注册类的方法和系统
公开(公告)号：WO2005098619A1
公开(公告)日：2005-10-20
申请号：PCT/US2005/010712
申请日：2005-03-30
申请人： INTEL CORPORATION , HUANG, Bo , DAI, Jinquan , SEED, Cotton
发明人： HUANG, Bo , DAI, Jinquan , SEED, Cotton
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.
摘要翻译：提出了一种方法，包括在至少一个指令中将第一寄存器类分配给至少一个符号寄存器，确定第二寄存器类并将其分配给至少一个寄存器，减少寄存器类修正并重命名至少一个符号寄存器。还提出了一种系统，其包括具有至少一个寄存器的处理器和在处理器中执行的编译器，其输入具有许多操作块的源程序。编译器将至少一个指令中的第一寄存器类分配给至少一个符号寄存器，确定并将第二寄存器类分配给至少一个符号寄存器，减少寄存器类修正，并重命名至少一个符号寄存器。

10. 发明申请

WO2005050451A1 MEMORY ACCESS INSTRUCTION VECTORIZATION 审中-公开
标题翻译：存储器访问指令验证
公开(公告)号：WO2005050451A1
公开(公告)日：2005-06-02
申请号：PCT/CN2003/000989
申请日：2003-11-24
申请人： INTEL CORPORATION , INTEL CHINA LTD. , HUANG, Bo , LI, Long, (Paul) , DAI, Jinquan, (Jason) , HARRISON, Luddy, (Williams)
发明人： HUANG, Bo , LI, Long, (Paul) , DAI, Jinquan, (Jason) , HARRISON, Luddy, (Williams)
IPC分类号： G06F12/00
CPC分类号： G06F8/41
摘要： A compilation method includes converting memory access instructions that read or write less than a minimum data access unit (MDAU) to memory access instructions that read or write a multiple of the minimum data access unit, converting the memory access instructions into a format including a base address plus an offset, grouping subsets of the converted memory access instructions into partitions, and vectorizing the converted memory access instructions in the subsets that match instruction patterns.
摘要翻译：编译方法包括将读取或写入小于最小数据存取单元（MDAU）的存储器访问指令转换成读或写最小数据访问单元的倍数的存储器访问指令，将存储器访问指令转换成包括基底地址加偏移，将转换的存储器访问指令的子集分组成分区，以及对与指令模式匹配的子集中的转换的存储器访问指令进行向量化。

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