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1. 发明申请

WO2005098619A1 A METHOD AND SYSTEM FOR ASSIGNING REGISTER CLASS THROUGH EFFICIENT DATAFLOW ANALYSIS 审中-公开
标题翻译：一种通过有效数据流分析来注册注册类的方法和系统
公开(公告)号：WO2005098619A1
公开(公告)日：2005-10-20
申请号：PCT/US2005/010712
申请日：2005-03-30
申请人： INTEL CORPORATION , HUANG, Bo , DAI, Jinquan , SEED, Cotton
发明人： HUANG, Bo , DAI, Jinquan , SEED, Cotton
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.
摘要翻译：提出了一种方法，包括在至少一个指令中将第一寄存器类分配给至少一个符号寄存器，确定第二寄存器类并将其分配给至少一个寄存器，减少寄存器类修正并重命名至少一个符号寄存器。还提出了一种系统，其包括具有至少一个寄存器的处理器和在处理器中执行的编译器，其输入具有许多操作块的源程序。编译器将至少一个指令中的第一寄存器类分配给至少一个符号寄存器，确定并将第二寄存器类分配给至少一个符号寄存器，减少寄存器类修正，并重命名至少一个符号寄存器。

2. 发明申请

WO2005050445A2 AN APPARATUS AND METHOD FOR AN AUTOMATIC THREAD-PARTITION COMPILER 审中-公开
标题翻译：一种用于自动线程分割编译器的装置和方法
公开(公告)号：WO2005050445A2
公开(公告)日：2005-06-02
申请号：PCT/US2004/037161
申请日：2004-11-05
申请人： INTEL CORPORATION , LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
发明人： LI, Long , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F9/4843
摘要： In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as a respective threads of multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，描述了一种用于自动线程分区编译器的方法和装置。在一个实施例中，该方法包括将顺序应用程序转换成多个应用程序线程。一旦分区，多个应用程序线程作为多线程体系结构的相应线程同时执行。因此，并行多线程体系结构的性能改进是通过隐藏存储器访问延迟或通过将存储器访问与计算或其他存储器访问重叠来实现的。描述并要求保护其他实施例。

3. 发明申请

WO2005050444A3 AN APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELIZING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION 审中-公开
公开(公告)号：WO2005050444A3
公开(公告)日：2005-06-02
申请号：PCT/US2004/037160
申请日：2004-11-05
申请人： INTEL CORPORATION , DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
发明人： DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
IPC分类号： G06F9/45
摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

4. 发明授权

EP1683010B1 AN APPARATUS AND METHOD FOR AN AUTOMATIC THREAD-PARTITION COMPILER 有权
标题翻译：装置和方法用于自动线程划分编译
公开(公告)号：EP1683010B1
公开(公告)日：2009-12-30
申请号：EP04810519.1
申请日：2004-11-05
申请人： Intel Corporation
发明人： LI, Long, , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F9/4843

5. 发明授权

EP1730632B1 A METHOD AND SYSTEM FOR ASSIGNING REGISTER CLASS THROUGH EFFICIENT DATAFLOW ANALYSIS 有权
标题翻译：方法和系统来分配寄存器类别通过高效的数据流分析
公开(公告)号：EP1730632B1
公开(公告)日：2013-10-02
申请号：EP05733143.1
申请日：2005-03-30
申请人： Intel Corporation
发明人： HUANG, Bo , DAI, Jinquan , SEED, Cotton
IPC分类号： G06F9/45
CPC分类号： G06F8/441

6. 发明授权

EP1685483B1 AN APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELISING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION 有权
标题翻译： DEVICE AND METHOD FOR自动并行网络应用BY流水线变换
公开(公告)号：EP1685483B1
公开(公告)日：2008-11-26
申请号：EP04810518.3
申请日：2004-11-05
申请人： Intel Corporation
发明人： DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

7. 发明公开

EP1730632A1 A METHOD AND SYSTEM FOR ASSIGNING REGISTER CLASS THROUGH EFFICIENT DATAFLOW ANALYSIS 有权
标题翻译：方法和系统来分配寄存器类别通过高效的数据流分析
公开(公告)号：EP1730632A1
公开(公告)日：2006-12-13
申请号：EP05733143.1
申请日：2005-03-30
申请人： Intel Corporation
发明人： HUANG, Bo , DAI, Jinquan , SEED, Cotton
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.

8. 发明公开

EP1685483A2 AN APPARATUS AND METHOD FOR AUTOMATICALLY PARALLELISING NETWORK APPLICATIONS THROUGH PIPELINING TRANSFORMATION 有权
标题翻译： DEVICE AND METHOD FOR自动并行网络应用BY流水线变换
公开(公告)号：EP1685483A2
公开(公告)日：2006-08-02
申请号：EP04810518.3
申请日：2004-11-05
申请人： INTEL CORPORATION
发明人： DAI, Jinquan , HARRISON, William, III , HUANG, Bo , SEED, Cotton , LI, Long
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

9. 发明公开

EP1683010A2 AN APPARATUS AND METHOD FOR AN AUTOMATIC THREAD-PARTITION COMPILER 有权
标题翻译：装置和方法用于自动线程划分编译
公开(公告)号：EP1683010A2
公开(公告)日：2006-07-26
申请号：EP04810519.1
申请日：2004-11-05
申请人： INTEL CORPORATION
发明人： LI, Long, , SEED, Cotton , HUANG, Bo , HARRISON, William, III , DAI, Jinquan
IPC分类号： G06F9/45
CPC分类号： G06F8/456 , G06F9/4843
摘要： In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as a respective threads of multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.

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