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1. 发明申请

WO2014105150A1 APPARATUS AND METHOD FOR TRACKING TLB FLUSHES ON A PER THREAD BASIS 审中-公开
标题翻译：在每个螺纹基础上跟踪TLB冲洗的装置和方法
公开(公告)号：WO2014105150A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/046907
申请日：2013-06-20
申请人： INTEL CORPORATION , CONRAD, Shaun M. , FENGER, Russell J. , KHANNA, Gaurav , SETH, Rahul , CROSSLAND, James B. , AGGARWAL, Anil
发明人： CONRAD, Shaun M. , FENGER, Russell J. , KHANNA, Gaurav , SETH, Rahul , CROSSLAND, James B. , AGGARWAL, Anil
IPC分类号： G06F9/38 , G06F9/46 , G06F12/10
CPC分类号： G06F12/1027 , G06F1/3206 , G06F2212/683 , Y02D10/13
摘要： A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.
摘要翻译：描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。

2. 发明申请

WO2014051815A1 METHOD AND APPARATUS FOR EFFICIENT STORE/RESTORE OF STATE INFORMATION DURING A POWER STATE TRANSITION 审中-公开
标题翻译：在电力状态过渡期间有效存储/恢复状态信息的方法和装置
公开(公告)号：WO2014051815A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/048663
申请日：2013-06-28
申请人： INTEL CORPORATION , CONRAD, Shaun M. , BENDT, Jared E. , LAVAKUMAR, Janardhan
发明人： CONRAD, Shaun M. , BENDT, Jared E. , LAVAKUMAR, Janardhan
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3243 , G06F13/00 , Y02D10/126 , Y02D10/152 , Y02D10/172 , Y02D50/20
摘要： A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.
摘要翻译：描述了处理器，其具有具有从存储器接收信息的第一接口的简化电路，其描述：i）功率域的内部状态信息的各自的地址; ii）当功率域断电时存储内部状态信息的存储器的相应地址; 以及iii）用于在电力域断电时将功率域之间的状态信息和内部状态信息存储在哪里的元数据。

3. 发明申请

WO2014099026A1 CONTROLLING CONFIGURABLE PEAK PERFORMANCE LIMITS OF A PROCESSOR 审中-公开
标题翻译：控制处理器的可配置峰值性能限制
公开(公告)号：WO2014099026A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048455
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： SHRALL, Jeremy J. , GUNTHER, Stephen H. , SISTLA, Krishnakanth V. , WELLS, Ryan D. , CONRAD, Shaun M.
IPC分类号： G06F1/32 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3243 , G06F1/324 , G06F3/14 , Y02D10/152
摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。描述和要求保护其他实施例。

4. 发明申请

WO2014035542A1 PERFORMING CROSS-DOMAIN THERMAL CONTROL IN A PROCESSOR 审中-公开
标题翻译：在处理器中执行跨域热控制
公开(公告)号：WO2014035542A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/048045
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , DERR, Michael N. , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , CONRAD, Shaun M. , ANANTHAKRISHNAN, Avinash N.
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有至少一个核的执行指令的第一域和耦合到第一域并且包括至少一个非核心电路的第二域。这些域可以在独立频率下操作，并且耦合到域的功率控制单元可以包括热逻辑，以响应于第二域中的热事件的发生而引起第一域的频率的降低。描述和要求保护其他实施例。

5. 发明申请

WO2014105194A1 INDEPENDENT CONTROL OF PROCESSOR CORE RETENTION STATES 审中-公开
标题翻译：处理器核心保持状态的独立控制
公开(公告)号：WO2014105194A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048306
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： CONRAD, Shaun M. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , DEVAL, Anant S. , JAHAGIRDAR, Sanjeev S.
IPC分类号： G06F9/38 , G06F9/46 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/3243 , Y02D10/152 , Y02D10/172
摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值电压值，独立于第二电压调节器。存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。描述和要求保护其他实施例。

6. 发明申请

WO2014105200A1 APPARATUS AND METHOD TO MANAGE ENERGY USAGE OF A PROCESSOR 审中-公开
标题翻译：管理能源使用处理器的装置和方法
公开(公告)号：WO2014105200A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048416
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： CONRAD, Shaun M. , GUNTHER, Stephen H.
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3296 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor and a voltage regulator coupled to the processor, during a low power period according to a first voltage regulator control mode and a second voltage regulator control mode, and to control the voltage regulator based at least in part on the predicted energy usage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个处理器核心和具有能量使用逻辑的功率控制逻辑，以在根据第一电压调节器控制模式的低功率周期期间预测处理器的能量使用和耦合到处理器的电压调节器以及第二电压调节器控制模式，并且至少部分地基于所预测的能量使用来控制所述电压调节器。描述和要求保护其他实施例。

7. 发明申请

WO2014105198A1 INTERCONNECT TO COMMUNICATE INFORMATION UNI-DIRECTIONALLY 审中-公开
标题翻译：不间断地传播信息
公开(公告)号：WO2014105198A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048358
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： CONRAD, Shaun M. , KNOLLA, William , MORAN, Douglas R. , RAHMAN, SM M. , HAJ-YIHIA, Jawad , NAVEH, Alon , FALIK, Ohad
IPC分类号： G06F13/14 , G06F13/38 , G06F1/26
CPC分类号： G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
摘要： A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
摘要翻译：处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。描述和要求保护其他实施例。

8. 发明公开

EP3049887A1 IMPROVED POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS 审中-公开
标题翻译：改进的功率控制方法进行综合PCIE CONTROLS
公开(公告)号：EP3049887A1
公开(公告)日：2016-08-03
申请号：EP14849812.4
申请日：2014-09-16
申请人： Intel Corporation
发明人： SPRY, Bryan L. , LOOI, Lily P. , CONRAD, Shaun M.
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3253 , G06F1/3278 , Y02D10/151 , Y02D10/157 , Y02D10/171 , Y02D50/20
摘要： Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

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