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1. 发明申请

WO2014099026A1 CONTROLLING CONFIGURABLE PEAK PERFORMANCE LIMITS OF A PROCESSOR 审中-公开
标题翻译：控制处理器的可配置峰值性能限制
公开(公告)号：WO2014099026A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048455
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： SHRALL, Jeremy J. , GUNTHER, Stephen H. , SISTLA, Krishnakanth V. , WELLS, Ryan D. , CONRAD, Shaun M.
IPC分类号： G06F1/32 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3243 , G06F1/324 , G06F3/14 , Y02D10/152
摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。描述和要求保护其他实施例。

2. 发明申请

WO2013077890A1 COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT 审中-公开
标题翻译：协作处理器和系统性能和电源管理
公开(公告)号：WO2013077890A1
公开(公告)日：2013-05-30
申请号：PCT/US2011/068198
申请日：2011-12-30
申请人： INTEL CORPORATION , THERIEN, Guy M. , DIEFENBAUGH, Paul S. , AGGARWAL, Anil , HENROID, Andrew D. , SHRALL, Jeremy J. , ROTEM, Efraim , SISTLA, Krishnakanth V. , WEISSMANN, Eliezer
发明人： THERIEN, Guy M. , DIEFENBAUGH, Paul S. , AGGARWAL, Anil , HENROID, Andrew D. , SHRALL, Jeremy J. , ROTEM, Efraim , SISTLA, Krishnakanth V. , WEISSMANN, Eliezer
IPC分类号： G06F9/30 , G06F9/22 , G06F1/32
CPC分类号： G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172
摘要： The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
摘要翻译：平台电力管理方案技术领域本发明涉及一种平台电力管理方案。在一些实施例中，平台使用要由OSPM系统请求的一个或多个参数来提供相对性能等级。

3. 发明申请

WO2018063751A1 COMPENSATION CONTROL FOR VARIABLE POWER RAILS 审中-公开
标题翻译：变电铁路的补偿控制
公开(公告)号：WO2018063751A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050039
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , RADJAI, Amir Ali , SHRALL, Jeremy J.
IPC分类号： G06F1/32 , G06F15/78
CPC分类号： G06F1/28 , G05F1/625 , G06F1/305
摘要： In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一电源轨，耦合到第一电源轨的第一组件和补偿控制单元。补偿控制单元用于：检测将第一电力轨的电压电平改变第一电压改变量的请求; 响应于检测到所述请求，确定所述第一电压改变量超过与所述第一分量相关联的第一阈值水平; 并且响应于确定第一电压变化量超过第一阈值电平，在改变第一电力轨的电压电平之前启动第一补偿动作。描述并要求保护其他实施例。

4. 发明申请

WO2018044491A1 PROCESSOR TO PRE-EMPT VOLTAGE RAMPS FOR EXIT LATENCY REDUCTIONS 审中-公开
标题翻译：处理器预先施加电压，以降低出口延迟
公开(公告)号：WO2018044491A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/045253
申请日：2017-08-03
申请人： INTEL CORPORATION
发明人： ANANTHAKRISHNAN, Avinash N. , SHRALL, Jeremy J. , SURYANARAYANAN, Anupama , AMBARDEKAR, Ameya , TOPPER, Craig , HEIT, Eric R. , ALBERTS, Joseph M.
IPC分类号： G06F1/32 , G06F9/50
摘要： In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和功率控制器。该功率控制器又可包括电压斜坡逻辑，以响应于对第二核心退出低功率状态的请求，将电压调节器的电压斜坡从第一电压预充电至第二电压。描述并要求保护其他实施例。

5. 发明申请

WO2014035542A1 PERFORMING CROSS-DOMAIN THERMAL CONTROL IN A PROCESSOR 审中-公开
标题翻译：在处理器中执行跨域热控制
公开(公告)号：WO2014035542A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/048045
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , DERR, Michael N. , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , CONRAD, Shaun M. , ANANTHAKRISHNAN, Avinash N.
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有至少一个核的执行指令的第一域和耦合到第一域并且包括至少一个非核心电路的第二域。这些域可以在独立频率下操作，并且耦合到域的功率控制单元可以包括热逻辑，以响应于第二域中的热事件的发生而引起第一域的频率的降低。描述和要求保护其他实施例。

6. 发明申请

WO2013090348A1 A METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING CONFIGURABLE MAXIMUM PROCESSOR CURRENT 审中-公开
标题翻译：一种用于能源效率和能源保护的方法，装置和系统，包括可配置的最大处理器电流
公开(公告)号：WO2013090348A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/069121
申请日：2012-12-12
申请人： INTEL CORPORATION , SHAH, Ketan R. , DISTEFANO, Eric , GUNTHER, Stephen H. , SHRALL, Jeremy J.
发明人： SHAH, Ketan R. , DISTEFANO, Eric , GUNTHER, Stephen H. , SHRALL, Jeremy J.
IPC分类号： G06F13/14 , G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F9/4401 , G06F9/4411 , G06F9/455 , Y02D10/126 , Y02D10/152 , Y02D50/20
摘要： An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform.
摘要翻译：本文描述了一种用于提供多个最大电流配置选项的装置，方法和系统，包括用于处理设备的对应的turbo频率。处理器的可用选项由初始化代码确定。并且基于平台电气功能，选择多个当前配置选项中的最佳一个。此外，在运行期间，基于当前配置注意事项动态地选择当前配置，以提供每个部件和计算平台的高灵活性和最佳性能。

7. 发明公开

EP3238003A1 POWER MANAGEMENT IN AN UNCORE FABRIC 审中-公开
标题翻译：电源管理在一个UNCORE织物
公开(公告)号：EP3238003A1
公开(公告)日：2017-11-01
申请号：EP15874062.1
申请日：2015-11-28
申请人： Intel Corporation
发明人： NAGARAJAN, Ramadass , SHRALL, Jeremy J. , HALLNOR, Erik G. , ABRAHAM, Vinit Mathew , HARRINGTON, Ezra N.
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3287 , G06F1/28 , G06F1/3206 , G06F1/3237 , G06F1/3253 , Y02D10/171
摘要： In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.
摘要翻译：在一个示例中，片上系统（SoC）的共享非核存储结构被配置为提供实时电力管理。 SoC可以包括电源管理代理以通知共享结构处理内核和外围设备一段时间将空闲并协商节能状态。非核心结构还可以包括本地电源管理器，该电源管理器检测一段时间内未接收到访问请求的时间，例如核心从高速缓存运行时。共享结构然后可以单方面进入节能状态，并保持该状态直到接收到访问请求。在省电状态下，电源和/或时钟被门控，并且结构的状态被存储在保留单元中。当接收到新的访问请求时，非本地控制器可以处理初步处理，而本地电源管理器恢复状态并启动共享架构。

8. 发明申请

WO2018063750A1 GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA 审中-公开
标题翻译：用平均数据产生处理器中断
公开(公告)号：WO2018063750A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050036
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , SHRALL, Jeremy J. , GANAPATHY, Deepak , SHAPIRA, Dorit
IPC分类号： G06F9/48
摘要： In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个执行单元以及中断产生单元。中断产生单元可以用于：在第一时间窗口上的多个时间点接收指示用于存储器单元的热状态值的多个值; 基于指示存储器单元中的热状态值的多个值来确定运行平均值; 并且响应于确定运行平均值已经超过高热状态阈值，生成指示处理器中的高热状态事件的热中断。描述并要求保护其他实施例。

9. 发明申请

WO2014105194A1 INDEPENDENT CONTROL OF PROCESSOR CORE RETENTION STATES 审中-公开
标题翻译：处理器核心保持状态的独立控制
公开(公告)号：WO2014105194A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048306
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： CONRAD, Shaun M. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , DEVAL, Anant S. , JAHAGIRDAR, Sanjeev S.
IPC分类号： G06F9/38 , G06F9/46 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/3243 , Y02D10/152 , Y02D10/172
摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值电压值，独立于第二电压调节器。存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。描述和要求保护其他实施例。

10. 发明申请

WO2014084842A1 ENFORCING A POWER CONSUMPTION DUTY CYCLE IN A PROCESSOR 审中-公开
标题翻译：执行处理器中的功耗周期
公开(公告)号：WO2014084842A1
公开(公告)日：2014-06-05
申请号：PCT/US2012/067202
申请日：2012-11-30
申请人： INTEL CORPORATION
发明人： VARMA, Ankush , SISTLA, Krishnakanth , ROWLAND, Martin T. , GRIFFITH, Brian J. , VOGMAN, Viktor D. , DOUCETTE, Joseph R. , DEHAEMER, Eric J. , GARG, Vivek , POIRIER, Chris , SHRALL, Jeremy J. , ANANTHAKRISHNAN, Avinash N. , GUNTHER, Stephen H.
IPC分类号： G06F1/26
CPC分类号： G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
摘要： In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上工作周期的占空比部分。描述和要求保护其他实施例。

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