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1. 发明申请

WO2018005100A1 APPARATUSES, METHODS, AND SYSTEMS FOR PACKAGE ON PACKAGE MEMORY REFRESH AND SELF-REFRESH RATE MANAGEMENT 审中-公开
标题翻译：用于封装存储器刷新和自刷新率管理的装置，方法和系统
公开(公告)号：WO2018005100A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037514
申请日：2017-06-14
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , KULICK, Stanley S.
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G06F15/786 , G11C11/40615
摘要： Methods, systems, and apparatuses relating to package on package memory refresh and self-refresh rate management are described. In one embodiment, an apparatus includes a processor die, a dynamic memory die mounted to and overlapping the processor die, a first thermal sensor of the processor die disposed adjacent to a first hot spot from a first type of workload and a second thermal sensor of the processor die disposed adjacent to a second hot spot from a second type of workload, and a hardware control circuit of the processor die to cause a refresh of a capacitor of the dynamic memory die when either of an output of the first thermal sensor exceeds a first threshold value and an output of the second thermal sensor exceeds a second threshold value.
摘要翻译：描述了与封装式存储器刷新和自刷新率管理相关的方法，系统和装置。在一个实施例中，一种装置包括处理器管芯，安装到处理器管芯并与处理器管芯重叠的动态存储器管芯，处理器管芯的第一热传感器与第一类型工作负载的第一热点相邻设置，以及第二热传感器为所述处理器管芯设置在来自第二类型工作负载的第二热点附近，以及所述处理器管芯的硬件控制电路，以在所述第一热传感器的输出中的任一者超过所述动态存储器管芯的电容器时使所述动态存储器管芯的电容器更新第一阈值和第二热传感器的输出超过第二阈值。

2. 发明申请

WO2018063750A1 GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA 审中-公开
标题翻译：用平均数据产生处理器中断
公开(公告)号：WO2018063750A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050036
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , SHRALL, Jeremy J. , GANAPATHY, Deepak , SHAPIRA, Dorit
IPC分类号： G06F9/48
摘要： In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个执行单元以及中断产生单元。中断产生单元可以用于：在第一时间窗口上的多个时间点接收指示用于存储器单元的热状态值的多个值; 基于指示存储器单元中的热状态值的多个值来确定运行平均值; 并且响应于确定运行平均值已经超过高热状态阈值，生成指示处理器中的高热状态事件的热中断。描述并要求保护其他实施例。

3. 发明申请

WO2014004510A1 MECHANISM TO PROVIDE WORKLOAD AND CONFIGURATION-AWARE DETERMINISTIC PERFORMANCE FOR MICROPROCESSORS 审中-公开
标题翻译：为微处理器提供工作负载和配置 - 确定性能的机制
公开(公告)号：WO2014004510A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/047620
申请日：2013-06-25
申请人： INTEL CORPORATION
发明人： VARMA, Ankush , SISTLA, Krishnakanth V. , ROWLAND, Martin T. , POIRIER, Chris , DEHAEMER, Eric J. , ANANTHAKRISHNAN, Avinash N. , SHRALL, Jeremy J. , MAN, Xiuting C. , GUNTHER, Stephen H. , RANGAN, Krishna K. , BODAS, Devadatta V. , SOLTIS, Don , NGUYEN, Hang T. , WOO, Cyprian W. , DANG, Thi
IPC分类号： G06F1/00 , G06F1/26 , G06F9/44
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/28 , G06F1/3206 , Y02D10/152
摘要： An apparatus that includes a semiconductor chip having a processor and an on-die non-volatile storage resource is described. The on-die non volatile storage is to store different, appropriate performance related information for different configurations and/or usage cases of the processor for a same performance state of the processor.
摘要翻译：描述了包括具有处理器和裸片上非易失性存储资源的半导体芯片的装置。在线非易失性存储器是为处理器的相同性能状态存储用于处理器的不同配置和/或使用情况的不同的适当的性能相关信息。

4. 发明申请

WO2018063751A1 COMPENSATION CONTROL FOR VARIABLE POWER RAILS 审中-公开
标题翻译：变电铁路的补偿控制
公开(公告)号：WO2018063751A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/050039
申请日：2017-09-05
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , RADJAI, Amir Ali , SHRALL, Jeremy J.
IPC分类号： G06F1/32 , G06F15/78
CPC分类号： G06F1/28 , G05F1/625 , G06F1/305
摘要： In an embodiment, a processor includes a first power rail, a first component coupled to the first power rail, and a compensation control unit. The compensation control unit is to: detect a request to change a voltage level of the first power rail by a first voltage change amount; in response to detecting the request, determine that the first voltage change amount exceeds a first threshold level associated with the first component; and in response to determining that the first voltage change amount exceeds the first threshold level, initiate a first compensation action prior to changing the voltage level of the first power rail. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一电源轨，耦合到第一电源轨的第一组件和补偿控制单元。补偿控制单元用于：检测将第一电力轨的电压电平改变第一电压改变量的请求; 响应于检测到所述请求，确定所述第一电压改变量超过与所述第一分量相关联的第一阈值水平; 并且响应于确定第一电压变化量超过第一阈值电平，在改变第一电力轨的电压电平之前启动第一补偿动作。描述并要求保护其他实施例。

5. 发明申请

WO2014035542A1 PERFORMING CROSS-DOMAIN THERMAL CONTROL IN A PROCESSOR 审中-公开
标题翻译：在处理器中执行跨域热控制
公开(公告)号：WO2014035542A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/048045
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , DERR, Michael N. , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , CONRAD, Shaun M. , ANANTHAKRISHNAN, Avinash N.
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有至少一个核的执行指令的第一域和耦合到第一域并且包括至少一个非核心电路的第二域。这些域可以在独立频率下操作，并且耦合到域的功率控制单元可以包括热逻辑，以响应于第二域中的热事件的发生而引起第一域的频率的降低。描述和要求保护其他实施例。

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