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1. 发明申请

WO2017019192A1 MASKING A POWER STATE OF A CORE OF A PROCESSOR 审中-公开
标题翻译：掩饰处理器核心的电源状态
公开(公告)号：WO2017019192A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/037347
申请日：2016-06-14
申请人： INTEL CORPORATION
发明人： GENDLER, Alexander , NOVAKOVSKY, Larisa , SISTLA, Krishnakanth V. , GARG, Vivek , MULLA, Dean , CHOUBAL, Ashish V. , HALLNOR, Erik G. , WEIER, Kimberly C.
IPC分类号： G06F1/32 , G06F13/14 , G06F9/38 , G06F15/78
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/26 , G06F1/263 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3293 , G06F9/38 , G06F15/17 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/24 , Y02D50/20
摘要： In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的核心和耦合到核心的核心周边逻辑。核心周界逻辑可以包括耦合到核的结构接口逻辑。反过来，结构接口逻辑可以包括第一存储器，以在核心处于低功率状态时存储核心的状态信息，并且使得耦合在核心和核心之间的管芯间互连能够被维持在活动状态在核心进入低功率状态期间。描述和要求保护其他实施例。

2. 发明申请

WO2017003602A1 TRACKING MISSED PERIODIC ACTIONS ACROSS STATE DOMAINS 审中-公开
标题翻译：追踪国家域名的错误定期行为
公开(公告)号：WO2017003602A1
公开(公告)日：2017-01-05
申请号：PCT/US2016/034291
申请日：2016-05-26
申请人： INTEL CORPORATION , MULLA, Dean , BORKOWSKI, Daniel G. , SISTLA, Krishnakanth V. , WU, Victor , LUTHRA, Manev
发明人： MULLA, Dean , BORKOWSKI, Daniel G. , SISTLA, Krishnakanth V. , WU, Victor , LUTHRA, Manev
IPC分类号： G06F11/30 , G06F11/07 , G06F13/16
CPC分类号： G06F1/3296 , G06F1/3225 , G06F1/3237 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/0653 , G06F3/0673 , Y02D10/128 , Y02D10/14 , Y02D10/172
摘要： Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.
摘要翻译：系统和方法可以提供用于在管理第二域的状态的第一域中确定第二域处于该状态，并且在第一域中确定周期性动作已被调度出现在第二域中而第二个域处于状态。此外，周期性动作可以被记录为关于第二域的错过事件。在一个示例中，将周期性动作记录为错过事件包括增加错过的事件计数器。

3. 发明申请

WO2013048794A1 DYNAMICALLY ADJUSTING POWER OF NON-CORE PROCESSOR CIRCUITRY 审中-公开
标题翻译：非核心处理器电路动态调整功能
公开(公告)号：WO2013048794A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/055702
申请日：2012-09-17
申请人： INTEL CORPORATION
发明人： SISTLA, Krishnakanth , MULLA, Dean , GARG, Vivek , ROWLAND, Mark , DORAISWAMY, Suresh , SRINIVASA, Ganapati , GILBERT, Jeffrey D.
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F15/80 , G06F13/14
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。描述和要求保护其他实施例。

4. 发明申请

WO2016105643A1 SYSTEMS AND METHODS FOR CORE DROOP MITIGATION BASED ON LICENSE STATE 审中-公开
标题翻译：基于许可证的核心减缓系统和方法
公开(公告)号：WO2016105643A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/055138
申请日：2015-10-12
申请人： INTEL CORPORATION
发明人： HAIDER, Nazar S. , MULLA, Dean , CHU, Allen W.
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , Y02D10/152
摘要： Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.
摘要翻译：公开了用于减轻计算设备中的电压下降的系统，方法和设备。示例性装置包括多个阈值寄存器以存储相应的电压下降阈值，以及接口，用于接收指示处理器核心或域的许可模式的许可证许可消息。许可证模式对应于处理器核心或域中所选择的一组执行单元。该设备还包括一个电压下降校正模块，用于根据许可证许可消息中指示的许可模式，从多个电压下降寄存器中选择一个电压下降阈值，并将处理器核心或域中的电压下降与所选择的电压下降阈值。基于比较，该装置触发电压下降校正处理。

5. 发明申请

WO2007016395A3 COMPUTING SYSTEM FEATURE ACTIVATION MECHANISM 审中-公开
公开(公告)号：WO2007016395A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/029529
申请日：2006-07-27
申请人： INTEL CORPORATION , MULLA, Dean , KHANNA, Rahul , PFLEDERER, Keith
发明人： MULLA, Dean , KHANNA, Rahul , PFLEDERER, Keith
IPC分类号： G06F21/02 , G06F21/20
摘要： Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.

6. 发明申请

WO2022067120A1 HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2022067120A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/052085
申请日：2021-09-24
申请人： INTEL CORPORATION
发明人： GARG, Vivek , VARMA, Ankush , SISTLA, Krishnakanth , GUPTA, Nikhil , BALIGAR, Nikethan Shivanand , WANG, Stephen , PALIT, Nilanjan , KAM, Timothy , PURANDARE, Adwait , GUPTA, Ujjwal , CHEN, Stanley , SHAPIRA, Dorit , VENUGOPAL, Shruthi , CHEMUDUPATI, Suresh , PARIKH, Rupal , DEHAEMER, Eric , SAMPATH, Pavithra , KANDULA, Phani Kumar , BANSAL, Yogesh , MULLA, Dean , TULANOWSKI, Michael , HAAKE, Stephen , HERDRICH, Andrew , DAS, Ripan
IPC分类号： G06F1/3203 , G06F1/30 , G06F1/26 , G06F9/50
摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

7. 发明申请

WO2017105734A1 CONTROLLING TELEMETRY DATA COMMUNICATION IN A PROCESSOR 审中-公开
标题翻译：控制处理器中的遥测数据通信
公开(公告)号：WO2017105734A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/062175
申请日：2016-11-16
申请人： INTEL CORPORATION
发明人： GARG, Vivek , GENDLER, Alexander , RAMAN, Arvind , CHOUBAL, Ashish V. , SISTLA, Krishnakanth V. , MULLA, Dean , DEHAEMER, Eric J. , AGRAWAL, Rahul , SOTOMAYOR, Guy G.
IPC分类号： G06F9/38
CPC分类号： G06F1/26 , G06F1/3243 , Y02D10/152
摘要： In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括用于执行指令的核心。至少一些核心包括遥测数据控制逻辑，用于根据交错时间表将第一遥测数据分组发送到功率控制器以防止数据冲突，以及全局对准计数器对交错对准时间段进行计数。描述并要求保护其他实施例。

8. 发明申请

WO2013165357A1 MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS 审中-公开
标题翻译：用于协调无障碍和集群系统中的空闲电源管理的主从QPI协议
公开(公告)号：WO2013165357A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/035827
申请日：2012-04-30
申请人： INTEL CORPORATION , GARG, Vivek , SISTLA, Krishnakanth , BLANKENSHIP, Robert , MULLA, Dean , BORKOWSKI, Daniel G. , CONRAD, Shaun , SRINIVASA, Ganapati
发明人： GARG, Vivek , SISTLA, Krishnakanth , BLANKENSHIP, Robert , MULLA, Dean , BORKOWSKI, Daniel G. , CONRAD, Shaun , SRINIVASA, Ganapati
IPC分类号： G06F1/32 , G06F15/80 , G06F13/14
CPC分类号： G06F1/3203 , G06F1/3234 , Y02D50/20
摘要： Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner. Communications between the entities is facilitated using messages transported over existing interconnects and corresponding protocols, enabling the benefits associated with the disclosed embodiments to be implemented using existing designs.
摘要翻译：在无缝和集群系统中实现协调空闲电源管理的方法，设备和系统。在诸如服务器平台的无胶纸系统中的用于促进协调包间歇功率状态的组件包括一个插座（即，处理器）中的主实体和参与电力管理协调的每个插座中的从实体。每个从机从各种来源收集空闲状态输入，当插座内核足够空闲时，它要求主机进入更深的空闲电源状态。主机响应于从机请求来协调全局功率管理操作，包括向所有从机广播具有目标延迟的命令，以允许处理器以协调的方式进入降低的功率（即空闲）状态。使用通过现有互连和相应协议传输的消息来促进实体之间的通信，从而能够使用现有设计实现与公开的实施例相关联的益处。

10. 发明公开

EP3314439A1 TRACKING MISSED PERIODIC ACTIONS ACROSS STATE DOMAINS 有权
标题翻译：跟踪状态域中的错误周期性操作
公开(公告)号：EP3314439A1
公开(公告)日：2018-05-02
申请号：EP16818411.7
申请日：2016-05-26
申请人： Intel Corporation
发明人： MULLA, Dean , BORKOWSKI, Daniel G. , SISTLA, Krishnakanth V. , WU, Victor , LUTHRA, Manev
IPC分类号： G06F11/30 , G06F11/07 , G06F13/16
CPC分类号： G06F1/3296 , G06F1/3225 , G06F1/3237 , G06F1/3275 , G06F3/0604 , G06F3/0625 , G06F3/0653 , G06F3/0673 , G06F11/106 , Y02D10/128 , Y02D10/14 , Y02D10/172
摘要： Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

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