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1. 发明专利

AU2021103735A4 A HONEYPOT BASED NETWORK SECURITY SYSTEM 未知
公开(公告)号：AU2021103735A4
公开(公告)日：2021-08-26
申请号：AU2021103735
申请日：2021-06-30
申请人： AGRAWAL CHAITANYA P , ARORA SANGEETA , GARG VIVEK , HARSHAVARDHAN A , MANARCAD PHILSON , PAUL BASIL , UPRETI KAMAL , VARGIS BINU KURIAKOSE
发明人： VARGIS BINU KURIAKOSE , UPRETI KAMAL , MANARCAD PHILSON , GARG VIVEK , HARSHAVARDHAN A , PAUL BASIL , AGRAWAL CHAITANYA P , ARORA SANGEETA
IPC分类号： H04L29/06 , G06F21/50
摘要： A HONEYPOT BASED NETWORK SECURITY SYSTEM Aspects of the present disclosure relate to a honeypot based network security system (100) and a data processing method (200) thereof. In an aspect, the honeypot-based network 5 security system (100) comprises of: an attacking terminal (102) which sends a source data to the honeypot (104), and a honeypot (104) for acquiring the source data sent by the attacking terminal and comprising of bogus data. The method (200) of data processing on a honeypot-based network security system method comprises of: acquiring (202) a plurality of transmission control protocol (TCP) type source data set that are sent by the attack 10 terminal, simulating (204) a TCP protocol for constructing a TCP feedback data packet which meets the pre-set requirement, and sending (206) the TCP feedback data packet to the attack terminal. (FIG. 1 will be the reference figure) - 13 - Attacking Honeypot 102 Terminal 104 Hopeypot Database layer ____ ___ ____ ___ ___106 Firewall _____ ____ ____ ____108 Original Database layer ____ ____ ____ ____110 Basic Information Database 100 layer 112 Fig. 1 Block diagram of a honeypot based network security system. - 14 -

2. 发明专利

DE202022102590U1 Ein auf IoT und maschinellem Lernen basierendes intelligentes Sitzmöbel-System 未知
公开(公告)号：DE202022102590U1
公开(公告)日：2022-07-07
申请号：DE202022102590
申请日：2022-05-12
申请人： BHATIA PRAMOD , BHATIA SUMAN , CHABA YOGESH , DEMBLA DEEPAK , GARG VIVEK , GOYAL VISHAL , JAIN BHARAT BHUSHAN , JECRC UNIV , JHA PRADEEP , SHEKHAR SHEKHAR , TINKER SEEMA , TOMAR SANDEEP
IPC分类号： G06Q10/08 , A61G1/00 , G06N3/02 , G06N20/00 , G16H40/20 , G16Y10/60
摘要： Ein auf IoT und maschinellem Lernen basierendes intelligentes Trage- und Stuhlsystem, das System umfasst:eine Stromversorgungseinheit zur Stromversorgung des intelligenten Trage-StuhlSystems, wobei die Trage über ein Solarzellen-Lademodul mit Batterien betrieben wird;eine Touchscreen-Bedienoberfläche zum Anrufen einer freien intelligenten Krankentrage, die von einer autorisierten Person im Krankenhaus durch Drücken der Ruftaste auf der verfügbaren Touchscreen-Bedienoberfläche angerufen werden kann;eine Objekterkennungseinheit zum Erkennen von Objekten und Hindernissen in der Nähe der Trage bzw. des Stuhls, wobei eine Vielzahl von Sensoren sowohl vor als auch hinter der Trage verwendet wird und sowohl als Empfänger als auch als Sender fungieren kann, und wobei ein IoT-Gerät zur Bestimmung der Position des Objekts verwendet wird;eine Bildverarbeitungseinheit zum Identifizieren des Hindernisses in der Nähe der Trage durch Erfassen der Bilder unter Verwendung einer Vielzahl von Kameras, wobei ein auf einem neuronalen Faltungsnetzwerk basierendes maschinelles Lernmodell zum Messen des Parkraums, der Größe und der Entfernung verwendet wird;eine Sprachsteuerungs-Verarbeitungseinheit zur Steuerung der Bewegung der Trage unter Verwendung des Sprachbefehls, wobei in diesem Modul eine auf der Architektur eines rekurrenten neuronalen Netzes (RNN) basierende maschinelle Lerntechnik verwendet wird;ein Gewichtsmessmodul zum Messen des Gewichts des Patienten unter Verwendung eines IoT-Geräts, wobei ein Gewichtssensor zum Messen des Gewichts der Patienten verwendet wird und wobei das Modul auf der Grundlage des Mindestschwellengewichts aktiviert wird; undein Radbewegungsmodul zur Steuerung der Bewegung der Räder unter Verwendung eines IoT-Geräts zur automatischen Radbewegung.

3. 发明专利

AU2021103287A4 COMPUTER IMPLEMENTED METHOD FOR SCANNING FOR DETERMINING CHARACTERISTICS OF MATERIALS USING ARTIFICIAL INTELLIGENCE 未知
公开(公告)号：AU2021103287A4
公开(公告)日：2021-08-05
申请号：AU2021103287
申请日：2021-06-10
申请人： GARG VIVEK , VARGIS BINU KURIAKOSE , BRADLEY MICHAEL
发明人： GARG VIVEK , VARGIS BINU KURIAKOSE , BRADLEY MICHAEL
IPC分类号： G06K9/62 , G06K9/00 , G06T1/00
摘要： COMPUTER IMPLEMENTED METHOD FOR SCANNING FOR DETERMINING CHARACTERISTICS OF MATERIALS USING ARTIFICIAL INTELLIGENCE The present invention relates to a computer implemented method for scanning for determining characteristics of materials using artificial intelligence. The objective of present invention is to solve the anomalies presented in the prior art techniques related to for scanning for determining characteristics of materials using computerized system. The computer implemented method comprises step of assisting a scanning unit to capture visual inputs of material samples placed on an internal surface of the scanning unit and analyzing using a machine learning based module to determine the characteristics of the materials. obtaining visual input of a material sample captured with a visual sensor of ahandheld computing unit that is configured on a scanning unit configured as a platform for uniformly capturing visual inputs of different material samples identify the characteristics of the material sample based on a combination of visual characteristics detected inthe captured visual entry of the material sample identify the characteristics of the sample material based on visual data

4. 发明申请

WO2013147801A1 DYNAMIC POWER LIMIT SHARING IN A PLATFORM 审中-公开
标题翻译：动态功率限制在平台中共享
公开(公告)号：WO2013147801A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031249
申请日：2012-03-29
申请人： INTEL CORPORATION , VARMA, Ankush , SISTLA, Krishnakanth , QUIROZ, Cesar , GARG, Vivek , ROWLAND, Martin , SODHI, Inder , BURNS, James
发明人： VARMA, Ankush , SISTLA, Krishnakanth , QUIROZ, Cesar , GARG, Vivek , ROWLAND, Martin , SODHI, Inder , BURNS, James
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
摘要翻译：一种用于在平台中的模块之间动态功率限制共享的方法和装置。在本发明的一个实施例中，平台包括处理器和存储器模块。通过扩展功率域以包括处理器和存储器模块，能够在处理器和存储器模块之间动态共享平台的功率预算。对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。这在本发明的一个实施例中能够实现相同的总平台功率预算的更高的峰值性能。

5. 发明申请

WO2012129147A2 MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中管理功耗
公开(公告)号：WO2012129147A2
公开(公告)日：2012-09-27
申请号：PCT/US2012/029604
申请日：2012-03-19
申请人： INTEL CORPORATION , FETZER, Eric , REIDLINGER, Reid J. , SOLTIS, Don , BOWHILL, William J. , SHRIMALI, Satish , SISTLA, Krishnakanth , ROTEM, Efraim , KUMAR, Rakesh , GARG, Vivek , NAVEH, Alon , SHARMA, Lokesh
发明人： FETZER, Eric , REIDLINGER, Reid J. , SOLTIS, Don , BOWHILL, William J. , SHRIMALI, Satish , SISTLA, Krishnakanth , ROTEM, Efraim , KUMAR, Rakesh , GARG, Vivek , NAVEH, Alon , SHARMA, Lokesh
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译：处理器可以包括核心和无孔区域。可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。结果，可以减少由无孔区域消耗的空闲功率。

6. 发明申请

WO2013165357A1 MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN GLUELESS AND CLUSTERED SYSTEMS 审中-公开
标题翻译：用于协调无障碍和集群系统中的空闲电源管理的主从QPI协议
公开(公告)号：WO2013165357A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/035827
申请日：2012-04-30
申请人： INTEL CORPORATION , GARG, Vivek , SISTLA, Krishnakanth , BLANKENSHIP, Robert , MULLA, Dean , BORKOWSKI, Daniel G. , CONRAD, Shaun , SRINIVASA, Ganapati
发明人： GARG, Vivek , SISTLA, Krishnakanth , BLANKENSHIP, Robert , MULLA, Dean , BORKOWSKI, Daniel G. , CONRAD, Shaun , SRINIVASA, Ganapati
IPC分类号： G06F1/32 , G06F15/80 , G06F13/14
CPC分类号： G06F1/3203 , G06F1/3234 , Y02D50/20
摘要： Methods, apparatus, and systems for implementing coordinated idle power management in glueless and clustered systems. Components for facilitating coordination of package idle power state between sockets in a glueless system such as a server platform include a master entity in one socket (i.e., processor) and a slave entity in each socket participating in the power management coordination. Each slave collects idle status inputs from various sources and when the socket cores are sufficiently idle, it makes a request to the master to enter a deeper idle power state. The master coordinates global power management operations in response to the slave requests, including broadcasting a command with a target latency to all of the slaves to allow the processors to enter reduced power (i.e., idle) states in a coordinated manner. Communications between the entities is facilitated using messages transported over existing interconnects and corresponding protocols, enabling the benefits associated with the disclosed embodiments to be implemented using existing designs.
摘要翻译：在无缝和集群系统中实现协调空闲电源管理的方法，设备和系统。在诸如服务器平台的无胶纸系统中的用于促进协调包间歇功率状态的组件包括一个插座（即，处理器）中的主实体和参与电力管理协调的每个插座中的从实体。每个从机从各种来源收集空闲状态输入，当插座内核足够空闲时，它要求主机进入更深的空闲电源状态。主机响应于从机请求来协调全局功率管理操作，包括向所有从机广播具有目标延迟的命令，以允许处理器以协调的方式进入降低的功率（即空闲）状态。使用通过现有互连和相应协议传输的消息来促进实体之间的通信，从而能够使用现有设计实现与公开的实施例相关联的益处。

7. 发明申请

WO2013101225A1 MICROPROCESSOR-ASSISTED AUTO-CALIBRATION OF VOLTAGE REGULATORS 审中-公开
标题翻译：微处理器辅助电压调节器的自动校准
公开(公告)号：WO2013101225A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068228
申请日：2011-12-30
申请人： INTEL CORPORATION , VARMA, Ankush , SCHRALL, Jeremy J. , SISTLA, Krishnakanth Venkata , ANANTHAKRISHNAN, Avinash N. , GARG, Vivek , POIRIER, Christopher , ROWLAND, Martin T , STANFORD, Edward R
发明人： VARMA, Ankush , SCHRALL, Jeremy J. , SISTLA, Krishnakanth Venkata , ANANTHAKRISHNAN, Avinash N. , GARG, Vivek , POIRIER, Christopher , ROWLAND, Martin T , STANFORD, Edward R
IPC分类号： G06F1/26 , G06F1/32 , G06F9/22
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F11/3024 , G06F11/3058
摘要： Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.
摘要翻译：处理器相对于为处理器供电的特定电压调节器的动态运行时校准，或耦合到处理器的存储器子系统可以减少或消除对电源管理计算中的保护带的需要。处理器从电压调节器接收电流测量值，并根据测量值和存储的预期值计算校准因子。校准因子可用于进行电源管理决策，而不是将保护带添加到功率读数。处理器的制造商或分销商可以使用具有比计算系统中使用的典型商用电源更高精度的受控电压源来计算存储值。所计算的存储值表示期望值，其可用于确定相对于有源系统的电压调节器的校准因子。

8. 发明申请

WO2013147849A1 DYNAMICALLY MEASURING POWER CONSUMPTION IN A PROCESSOR 审中-公开
标题翻译：在处理器中动态测量功耗
公开(公告)号：WO2013147849A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031464
申请日：2012-03-30
申请人： INTEL CORPORATION , VARMA, Ankush , SISTLA, Krishnakanth V. , ROWLAND, Martin T. , GARG, Vivek , BURNS, James S.
发明人： VARMA, Ankush , SISTLA, Krishnakanth V. , ROWLAND, Martin T. , GARG, Vivek , BURNS, James S.
IPC分类号： G01R31/28
CPC分类号： G01R21/133 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核以独立执行指令的处理器，第一传感器至少部分地基于在核上发生的事件来测量处理器的第一功率消耗水平，以及混合逻辑，第一功率消耗水平和第二功耗水平。描述和要求保护其他实施例。

9. 发明申请

WO2013095436A1 METHOD AND APPARATUS FOR SETTING AN I/O BANDWIDTH-BASED PROCESSOR FREQUENCY FLOOR 审中-公开
标题翻译：用于设置基于I / O带宽处理器频率地板的方法和装置
公开(公告)号：WO2013095436A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066488
申请日：2011-12-21
申请人： INTEL CORPORATION , VARMA, Ankush , STEINER, Ian M. , SISTLA, Krishnakanth V. , BACE, Matthew M. , GARG, Vivek , ROWLAND, Martin T. , WILDER, Jeffrey S.
发明人： VARMA, Ankush , STEINER, Ian M. , SISTLA, Krishnakanth V. , BACE, Matthew M. , GARG, Vivek , ROWLAND, Martin T. , WILDER, Jeffrey S.
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F1/324 , G06F13/382
摘要： An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.
摘要翻译：一种用于管理计算机处理器的频率的装置和方法。该装置包括用于管理计算机处理器中的电力的功率控制单元（PCU）。 PCU包括数据采集模块，用于从计算机处理器中的多个通信端口获取交易速率数据，以及耦合到数据收集模块的频率控制逻辑模块，频率控制逻辑来计算多个通信端口来处理流量，而不会显着增加延迟，并覆盖处理器互连频率以满足计算的最小处理器互连频率。

10. 发明申请

WO2012129147A3 MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：在多核处理器中管理功耗
公开(公告)号：WO2012129147A3
公开(公告)日：2013-03-14
申请号：PCT/US2012029604
申请日：2012-03-19
申请人： INTEL CORP , FETZER ERIC , REIDLINGER REID J , SOLTIS DON , BOWHILL WILLIAM J , SHRIMALI SATISH , SISTLA KRISHNAKANTH , ROTEM EFRAIM , KUMAR RAKESH , GARG VIVEK , NAVEH ALON , SHARMA LOKESH
发明人： FETZER ERIC , REIDLINGER REID J , SOLTIS DON , BOWHILL WILLIAM J , SHRIMALI SATISH , SISTLA KRISHNAKANTH , ROTEM EFRAIM , KUMAR RAKESH , GARG VIVEK , NAVEH ALON , SHARMA LOKESH
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , Y02B60/1217 , Y02B60/1285 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
摘要翻译：处理器可以包括核心和无孔区域。可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。结果，可以减少由无孔区域消耗的空闲功率。

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