专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2022067120A1 HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2022067120A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/052085
申请日：2021-09-24
申请人： INTEL CORPORATION
发明人： GARG, Vivek , VARMA, Ankush , SISTLA, Krishnakanth , GUPTA, Nikhil , BALIGAR, Nikethan Shivanand , WANG, Stephen , PALIT, Nilanjan , KAM, Timothy , PURANDARE, Adwait , GUPTA, Ujjwal , CHEN, Stanley , SHAPIRA, Dorit , VENUGOPAL, Shruthi , CHEMUDUPATI, Suresh , PARIKH, Rupal , DEHAEMER, Eric , SAMPATH, Pavithra , KANDULA, Phani Kumar , BANSAL, Yogesh , MULLA, Dean , TULANOWSKI, Michael , HAAKE, Stephen , HERDRICH, Andrew , DAS, Ripan
IPC分类号： G06F1/3203 , G06F1/30 , G06F1/26 , G06F9/50
摘要： Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

2. 发明申请

WO2018156153A1 CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS 审中-公开
公开(公告)号：WO2018156153A1
公开(公告)日：2018-08-30
申请号：PCT/US2017/019484
申请日：2017-02-24
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Vasudevan , SISTLA, Krishnakanth V. , GOUGH, Corey D. , STEINER, Ian M. , GUPTA, Nikhil , GARG, Vivek , VARMA, Ankush , VORA, Sujal A. , LERNER, David P. , SULLIVAN, Joseph M. , GURUMOORTHY , Nagasubramanian , BOWHILL, William J. , RAMAMURTHY , Venkatesh , MACNAMARA, Chris , BROWNE, John J. , DAS, Ripan
IPC分类号： G06F1/32 , G06F1/08 , G06F9/50
摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

3. 发明申请

WO2017112311A1 METHOD AND APPARATUS TO CONTROL NUMBER OF CORES TO TRANSITION OPERATIONAL STATES 审中-公开
标题翻译：控制核心数转换操作状态的方法和装置
公开(公告)号：WO2017112311A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063638
申请日：2016-11-23
申请人： INTEL CORPORATION
发明人： RAMAMURTHY, Venkatesh , DAS, Ripan
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3287 , Y02D10/171
摘要： An electronic device may be provided that includes logic, at least a portion which is hardware, to receive a plurality of transition requests within a configurable moving time period and to block a clock signal to one or more of the plurality of cores based on the received transition requests.
摘要翻译：可以提供一种电子设备，其包括逻辑，至少一部分是硬件，用于在可配置的移动时间段内接收多个转换请求并且将时钟信号阻挡到以下一个或多个：多个核心基于接收到的转换请求。

4. 发明申请

WO2014004035A2 CHARGING A BATTERY 审中-公开
标题翻译：充电电池
公开(公告)号：WO2014004035A2
公开(公告)日：2014-01-03
申请号：PCT/US2013/044587
申请日：2013-06-06
申请人： INTEL CORPORATION , DAS, Ripan , GURUMOORTHY, Nagasubramanian , KEATES, Andy
发明人： DAS, Ripan , GURUMOORTHY, Nagasubramanian , KEATES, Andy
IPC分类号： H02J7/04 , H02J7/00 , H02J13/00
CPC分类号： H02J7/045 , H02J7/041
摘要： A method and system for applying a multi-rate charge to a battery are included herein. The method includes detecting a plurality of predetermined electrical measurements and a plurality of predetermined charge currents. The method also includes detecting an electrical measurement of the battery. Additionally, the method includes selecting a charge current from the plurality of predetermined charge currents to be applied to the battery based on the electrical measurement of the battery and the plurality of predetermined electrical measurements. Furthermore, the method includes applying the charge current to the battery. The method also includes detecting a plurality of subsequent electrical measurements of the battery. In addition, the method includes applying a plurality of subsequent charge currents to the battery based on the plurality of subsequent electrical measurements of the battery and the plurality of predetermined charge currents.
摘要翻译：这里包括用于将多速率电荷施加到电池的方法和系统。该方法包括检测多个预定电测量和多个预定充电电流。该方法还包括检测电池的电测量。此外，该方法包括基于电池的电测量和多个预定电测量，从多个预定充电电流中选择要施加到电池的充电电流。此外，该方法包括将充电电流施加到电池。该方法还包括检测电池的多个随后的电测量。此外，该方法包括基于电池的多个随后的电测量和多个预定的充电电流将多个后续的充电电流施加到电池。

5. 发明公开

EP3394704A1 METHOD AND APPARATUS TO CONTROL NUMBER OF CORES TO TRANSITION OPERATIONAL STATES 审中-公开
公开(公告)号：EP3394704A1
公开(公告)日：2018-10-31
申请号：EP16879795.9
申请日：2016-11-23
申请人： Intel Corporation
发明人： RAMAMURTHY, Venkatesh , DAS, Ripan
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3287 , Y02D10/171
摘要： An electronic device may be provided that includes logic, at least a portion which is hardware, to receive a plurality of transition requests within a configurable moving time period and to block a clock signal to one or more of the plurality of cores based on the received transition requests.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式